66AK2L06_15 Datasheet, PDF (191/298 Pages) Texas Instruments – 66AK2L06 Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

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66AK2L06
SPRS930 – APRIL 2015
Figure 9-25. Power State Control Register (PWRSTATECTL)
31
Hibernation Recovery Branch Address
RW-0000 0000 0000 0000 0
Legend: R = Read Only, RW = Read/Write; -n = value after reset
3
2
1
Hibernation Mode
Hibernation
RW-0
RW-0
0
Standby
RW-0
Bit
31-3
2
Field
Hibernation
Recovery Branch
Address
Hibernation Mode
1
Hibernation
0
Standby
Table 9-41. Power State Control Register Field Descriptions
Description
Used to provide a start address for execution out of the hibernation modes. See the KeyStone Architecture
DSP Bootloader User's Guide (SPRUGY5).
Indicates whether the device is in hibernation mode 1 or mode 2.
• 0 = Hibernation mode 1
• 1 = Hibernation mode 2
Indicates whether the device is in hibernation mode or not.
• 0 = Not in hibernation mode
• 1 = Hibernation mode
Indicates whether the device is in standby mode or not.
• 0 = Not in standby mode
• 1 = standby mode
9.2.3.14 NMI Event Generation to C66x CorePac (NMIGRx) Register
NMIGRx registers generate NMI events to the corresponding C66x CorePac. The 66AK2L06 has four
NMIGRx registers (NMIGR0 through NMIGR3). The NMIGR0 register generates an NMI event to C66x
CorePac0. Writing a 1 to the NMIG field generates an NMI pulse. Writing a 0 has no effect and Reads
return 0 and have no other effect. The NMI event generation to the C66x CorePac is shown in Figure 9-26
and described in Table 9-42.
Figure 9-26. NMI Generation Register (NMIGRx)
31
Reserved
R-0000 0000 0000 0000 0000 0000 0000 000
Legend: RW = Read/Write; -n = value after reset
10
NMIG
RW-0
Bit
31-1
0
Field
Reserved
NMIG
Table 9-42. NMI Generation Register Field Descriptions
Description
Reserved
Reads return 0
Writes:
• 0 = No effect
• 1 = Creates NMI pulse to the corresponding C66x CorePac — C66x CorePac0 for NMIGR0, etc.
9.2.3.15 IPC Generation (IPCGRx) Registers
The IPCGRx Registers facilitate inter-C66x CorePac interrupts.
The 66AK2L06 device has six IPCGRx registers (IPCGR0 through IPCGR3 and IPCGR8 and IPCGR9).
These registers can be used by external hosts or CorePacs to generate interrupts to other CorePacs. A
write of 1 to the IPCG field of the IPCGRx register generates an interrupt pulse to the:
• C66x CorePacx (0 <= x <= 3)
• ARM CorePac core (8<=x<=9)
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