TMS416160 Datasheet, PDF (19/28 Pages) Texas Instruments – 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS

RAS
UCAS
LCAS
Address
W
DQ8 – DQ15
DQ0 – DQ7
OE
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRCD
tCRP
tCLCH
(see Note A)
tCSH
tCAS
tCP
tASR
tRAH
tASC
tCAH
Row
Column
Don’t Care
tRHCP
tRSH
tPC
tCAL
tRAL
Column
tRAD
Don’t
Care
tRCS
See Note D
See Note D
Don’t Care
tCLZ
tCAC
(see Note B)
tAA
tRAC
tCPA
(see Note C)
tOEA
Valid
Out
tAA
Valid
Out
tOEA
tOHO
Valid
Out
Don’t Care
tRCH
tOH
tRRH
Don’t
Care
tOFF
tOEZ
tOHO
Don’t Care
NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. tCAC is measured from xCAS to its corresponding DQx.
C. Access time is tCPA or tAA dependent.
D. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
E. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write-timing
specifications are not violated.
F. xCAS order is arbitrary.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
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