TCM320AC36 Datasheet, PDF (19/23 Pages) Texas Instruments – VOICE-BAND AUDIO PROCESSORS VBAPE

TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP™)
APPLICATION INFORMATION
SLWS003C – MAY 1992 – REVISED APRIL – 1998
output gain set design considerations (see Figure 7)
EARA and EARB are low-impedance complementary outputs. The voltages at the nodes are:
V_{O +} at EARA
V_{O –} at EARB
V_OD = V_{O +} – V_{O –} (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap connected to EARGS.
A value greater than 10 kΩ and less than 100 kΩ for R1 + R2 is recommended because of the following:
The parallel combination R1 + R2 and R_L sets the total loading. The total capacitance at EARGS and the
parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies.
V_A represents the maximum available digital mW output response (V_A = 0.751 Vrms).
V_OD = A × V_A
1 + (R1/R2)
where A = _{4 + (R1/R2)}
Digital mW Sequence
IAW CCITT G.712
2
EARA
4
DIN EARGS
3
EARB
R1
VO
R2
VO+
RL
VO _–
NOTE A: Terminal numbers shown are for the DW and N packages.
Figure 7. Gain-Setting Configuration
higher clock frequencies and sample rates
The VBAP is designed to work with sample rates up to 16 kHz where the frequency of the frame sync determines
the sampling frequency. However, there is a fundamental requirement to maintain the ratio of the master clock
frequency, f_CLK, to the frame sync frequency, f_FSR/f_FSX. This ratio for the VBAP is 2.048 MHz/8 kHz, or 256
master clocks per frame sync. For example, to operate the VBAP at a sampling rate of f_FSR and f_FSX equal to
16 kHz, f_CLK must be 256 times 16 kHz, or 4.096 MHz. If the VBAP is operated above an 8-kHz sample rate,
however, it is expected that the performance becomes somewhat degraded. Exact parametric specifications
for rates up to 16-kHz sample rate are not specified at this time.
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