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TCM320AC36 Datasheet, PDF (10/23 Pages) Texas Instruments – VOICE-BAND AUDIO PROCESSORS VBAPE | |||
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TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAPâ¢)
SLWS003C â MAY 1992 â REVISED APRIL â 1998
timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figure 1 through Figure 4)
MIN NOMâ MAX UNIT
tt
Transition time, CLK and DCLKX /DCLKR
Duty cycle, CLK
10 ns
45% 50% 55%
Duty cycle, DCLKX /DCLKR
â All typical values are at VCC = 5 V, TA = 25°C.
45% 50% 55%
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 2)
MIN MAX UNIT
tsu(FSX)
th(FSX)
Setup time, FSX high before CLKâ
Hold time, FSX high after CLKâ
20 468 ns
20 468 ns
receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 1)
tsu(FSR)
th(FSR)
tsu(DIN)
th(DIN)
Setup time, FSR high before CLKâ
Hold time, FSR high after CLKâ
Setup time, DIN high or low before CLKâ
Hold time, DIN high or low after CLKâ
MIN MAX UNIT
20 468 ns
20 468 ns
20
ns
20
ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 4)
tsu(FSX)
th(FSX)
Setup time, FSX high before DCLKXâ
Hold time, FSX high after DCLKXâ
MIN
MAX
40 tc(DCLKX)â 40
35 tc(DCLKX)â35
UNIT
ns
ns
receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 3)
tsu(FSR)
th(FSR)
tsu(DIN)
th(DIN)
Setup time, FSR high before DCLKRâ
Hold time, FSR high after DCLKRâ
Setup time, DIN high or low before DCLKRâ
Hold time, DIN high or low after DCLKRâ
MIN
MAX
40
35 tc(DCLKR)â35
30
30
UNIT
ns
ns
ns
ns
switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode,
CL = 0 to 10 pF (see Figure 2)
PARAMETER
TEST CONDITIONS
MIN MAX UNIT
tpd1 From CLK bit 1 high to DOUT bit 1 valid
tpd2 From CLK high to DOUT valid, bits 2 to n
tpd3 From CLK bit n low to DOUT bit n Hi-Z
tpd4 From CLK bit 1 high to TSX active (low)
tpd5 From CLK bit n low to TSX inactive (high)
Rpullup = 1.24 kâ¦
Rpullup = 1.24 kâ¦
35 ns
35 ns
30
ns
40 ns
30
ns
10
⢠POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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