TAS5076 Datasheet, PDF (19/62 Pages) Texas Instruments – SIX-CHANNEL DIGITAL AUDIO PWM PROCESSOR

2-Channel Left-Justified Stereo Input
32 Clks
LRCLK
Left Channel
SCLK
LRCLK
Architecture Overview
32 Clks
Right Channel
MSB
24-Bit Mode
23 22
98
54
10
LSB MSB
23 22
98
54
10
LSB
NOTE: All data presented in 2s complement form with MSB first.
Figure 2−5. Left-Justified 64-Fs Format
2-Channel Left-Justified Stereo Input/Output (24-Bit Transfer Word Size)
LRCLK
24 Clks
Left Channel
24 Clks
Right Channel
SCLK
MSB
24-Bit Mode
23 22 21 20 19
98
LSB MSB
5 4 3 2 1 0 23 22 21 20 19
98
Figure 2−6. Left-Justified 48-Fs Format
LSB
543210
2.1.7.3 Right-Justified Timing
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and
the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 48
or 64 times Fs is used to clock in the data. The first bit of data appears following the eighth bit-clock period
(for 24-bit data) after LRCLK toggles. In RJ mode, the last bit clock before LRCLK transitions always clocks
the LSB of data. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5076
masks unused leading data bit positions. Master mode only supports a 64 times Fs bit clock.
SLES090A—November 2003—Revised January 2004
TAS5076
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