TAS5076 Datasheet, PDF (17/62 Pages) Texas Instruments – SIX-CHANNEL DIGITAL AUDIO PWM PROCESSOR

Architecture Overview
2.1.6 DCLK
DCLK is the internal high-frequency clock that is produced by the PLL circuitry from MCLK. The TAS5076 uses
the DCLK to control all internal operations. DCLK is 8 times the speed of MCLK in normal speed mode, 4 times
MCLK in double speed, and 2 times MCLK in quad speed. With respect to the I²C addressable registers, DCLK
clock cycles are used to specify interchannel delay and to detect when the MCLK frequency is drifting.
Table 2−4 DCLK shows the relationship between sample rate, MCLK, and DCLK.
Table 2−4. DCLK
Fs
(kHz)
32
44.1
48
88
96
192
MCLK
(MHz)
8.1920
11.2896
12.2880
22.5280
24.5760
49.1520
DCLK
(MHz)
65.5360
90.3168
98.3040
90.1120
98.3040
98.3040
DCLK Period
(ns)
15.3
11.1
10.2
11.1
10.2
10.2
2.1.7 Serial Data Interface
The TAS5076 operates as a slave only/receive only serial data interface in all modes. The TAS5076 has three
PCM serial data interfaces to accept six channels of digital data though the SDIN1, SDIN2, SDIN3 inputs. The
serial audio data is in MSB-first, twos-complement format.
The serial data interfaces of the TAS5076 can be configured in right-justified, I²S, left-justified, or DSP modes.
This interface supports 32-kHz, 44.1-kHz, 48-kHz, 88-kHz, 96-kHz, 176.4-kHz, and 192-kHz data sample
rates. The serial data interface format is specified using the data interface control register. The supported word
lengths are shown in Table 2−5.
During normal operating conditions if the serial data interface settings change state, an error recovery
sequence is initiated.
Table 2−5. Supported Word Lengths
DATA MODES
WORD
LENGTHS
MOD2
MOD1
Right justified, MSB first
16
0
0
Right justified, MSB first
20
0
0
Right justified, MSB first
24
I2S
16
I2S
20
I2S
24
0
1
0
1
1
0
1
0
Left justified, MSB first
24
1
1
DSP frame
16
1
1
MOD0
0
1
0
1
0
1
0
1
2.1.7.1 I²S Timing
I²S timing uses LRCLK to define when the data being transmitted is for the left channel or the right channel.
LRCLK is low for the left channel and high for the right channel. A bit clock running at 48 or 64 times Fs is used
to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first
bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS5076 masks unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock.
SLES090A—November 2003—Revised January 2004
TAS5076
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