MSP430F42X_11 Datasheet, PDF (19/45 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − Ports P1 and P2; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
TEST CONDITIONS MIN TYP
V_IT+
Positive-going input threshold voltage
V_IT−
Negative-going input threshold voltage
V_hys
Input voltage hysteresis (V_IT+ − V_IT−)
V_CC = 3 V
V_CC = 3 V
V_CC = 3 V
1.5
0.9
0.45
MAX
1.98
1.3
1
UNIT
V
V
V
inputs Px.x, TAx
PARAMETER
t_(int)
External interrupt timing
t_(cap)
f_(TAext)
Timer_A, capture timing
Timer_A clock frequency
externally applied to pin
TEST CONDITIONS
V_CC
Port P1, P2: P1.x to P2.x, External trigger signal
3V
for the interrupt flag, (see Note 1)
3V
TAx
3V
TACLK, INCLK t_(H) = t_(L)
3V
MIN TYP MAX UNIT
1.5
cycle
50
ns
50
ns
10 MHz
f_(TAint)
NOTES:
Timer_A clock frequency
SMCLK or ACLK signal selected
3V
10 MHz
1. The external signal sets the interrupt flag every time the minimum t_(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t_(int). Both the cycle and timing specifications must be met to ensure the flag is set. t_(int) is measured in
MCLK cycles.
leakage current (see Note 1)
PARAMETER
TEST CONDITIONS
MIN NOM MAX
I_lkg(P1.x)
I_lkg(P2.x)
Leakage
current
Port P1 Port 1: V_(P1.x) (see Note 2)
Port P2 Port 2: V_(P2.x) (see Note 2)
V_CC = 3 V
±50
±50
NOTES: 1. The leakage current is measured with V_SS or V_CC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as an input.
UNIT
nA
outputs − Ports P1 and P2
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
I_OH(max) = −1.5 mA, V_CC = 3 V,
See Note 1 V_CC−0.25
V_CC
V_OH High-level output voltage
I_OH(max) = −6 mA,
V_CC = 3 V,
See Note 2
V_CC−0.6
V_CC
V_OL Low-level output voltage
I_OL(max) = 1.5 mA,
I_OL(max) = 6 mA,
V_CC = 3 V,
V_CC = 3 V,
See Note 1
See Note 2
V_SS
V_SS
V_SS+0.25
V_SS+0.6
NOTES:
1. The maximum total current, I_OH(max) and I_OL(max), for all outputs combined, should not exceed ±12 mA to satisfy the
maximum specified voltage drop.
2. The maximum total current, I_OH(max) and I_OL(max), for all outputs combined, should not exceed ±48 mA to satisfy the
maximum specified voltage drop.
UNIT
V
V
output frequency
PARAMETER
f_Px.y
f_ACLK,
f_MCLK,
f_SMCLK
(1 ≤ x ≤ 2, 0 ≤ y ≤ 7)
P1.1/TA0/MCLK
P1.5/TACLK/ACLK/S28
t_Xdc
Duty cycle of output frequency
TEST CONDITIONS
C_L = 20 pF,
I_L = ± 1.5mA
V_CC = 3 V
C_L = 20 pF
V_CC = 3 V
P1.5/TACLK/ACLK/
S28, C_L = 20 pF
V_CC = 3 V
P1.1/TA0/MCLK,
C_L = 20 pF,
V_CC = 3 V
f_ACLK = f_LFXT1 = f_XT1
f_ACLK = f_LFXT1 = f_LF
f_ACLK = f_LFXT1
f_MCLK = f_DCOCLK
MIN TYP
DC
MAX UNIT
12 MHz
12 MHz
40%
30%
50%−
15 ns
50%
50%
60%
70%
50%+
15 ns
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