BQ24740_07 Datasheet, PDF (19/32 Pages) Texas Instruments – Host-controlled Multi-chemistry Battery Charger with Low Input Power Detect

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bq24740
SLUS736 – DECEMBER 2006
CONVERTER OPERATION
The synchronous buck PWM converter uses a fixed frequency (300 kHz) voltage mode with feed-forward control
scheme. A type III compensation network allows using ceramic capacitors at the output of the converter. The
compensation input stage is connected internally between the feedback output (FBO) and the error amplifier
input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error
amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 8–12.5 kHz nominal.
Where
resonant
frequency,
f_o,
is
given
by:
f_o
+
1
2p ^ǸL_oC_{o where}
(from
Figure
1
schematic)
• C_O = C11 + C12
• L_O = L1
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is one-fifteenth of the input adapter voltage making it always directly proportional to
the input adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and
simplifies the loop compensation. The ramp is offset by 250 mV in order to allow zero percent duty-cycle, when
the EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order
to get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while
ensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin
voltage falls below 4 V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and
the low-side n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor.
Then the high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low
again due to leakage current discharging the BTST capacitor below the 4 V, and the reset pulse is reissued.
The 300 kHz fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input
voltage, battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of
the audible noise region. The charge current sense resistor R_SR should be placed with at least half or more of
the total output capacitance placed before the sense resistor contacting both sense resistor and the output
inductor; and the other half or remaining capacitance placed after the sense resistor. The output capacitance
should be divided and placed onto both sides of the charge current sense resistor. A ratio of 50:50 percent gives
the best performance; but the node in which the output inductor and sense resistor connect should have a
minimum of 50% of the total capacitance. This capacitance provides sufficient filtering to remove the switching
noise and give better current sense accuracy. The type III compensation provides phase boost near the
cross-over frequency, giving sufficient phase margin.
SYNCHRONOUS AND NON-SYNCHRONOUS OPERATION
The charger operates in non-synchronous mode when the sensed charge current is below the ISYNSET value.
Otherwise, the charger operates in synchronous mode.
During synchronous mode, the low-side n-channel power MOSFET is on, when the high-side n-channel power
MOSFET is off. The internal gate drive logic ensures there is break-before-make switching to prevent
shoot-through currents. During the 30ns dead time where both FETs are off, the back-diode of the low-side
power MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation
low, and allows safely charging at high currents. During synchronous mode the inductor current is always
flowing and operates in Continuous Conduction Mode (CCM), creating a fixed two-pole system.
During non-synchronous operation, after the high-side n-channel power MOSFET turns off, and after the
break-before-make dead-time, the low-side n-channel power MOSFET will turn-on for around 80ns, then the
low-side power MOSFET will turn-off and stay off until the beginning of the next cycle, where the high-side
power MOSFET is turned on again. The 80ns low-side MOSFET on-time is required to ensure the bootstrap
capacitor is always recharged and able to keep the high-side power MOSFET on during the next cycle. This is
important for battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a
voltage and can both source and sink current. The 80-ns low-side pulse pulls the PH node (connection between
high and low-side MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value.
After the 80 ns, the low-side MOSFET is kept off to prevent negative inductor current from occurring. The
inductor current is blocked by the off low-side MOSFET, and the inductor current will become discontinuous.
This mode is called Discontinuous Conduction Mode (DCM).
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