BQ24740_07 Datasheet, PDF (10/32 Pages) Texas Instruments – Host-controlled Multi-chemistry Battery Charger with Low Input Power Detect

bq24740
SLUS736 – DECEMBER 2006
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
7.0 V ≤ V_PVCC≤ 24 V, 0°C < T_J < +125°C, typical values are at T_A = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
QUIESCENT CURRENT
I_{OFF_STATE}
I_{BAT_ON}
I_{BAT_LOAD_CD}
I_{BAT_LOAD_CE}
I_AC
I_{AC_SWITCH}
Total off-state battery current from SRP,
SRN, BAT, VCC, BTST, PH, etc.
Battery on-state quiescent current
Internal battery load current, charge
disbled
Internal battery load current, charge
enabled
Adapter quiescent current
Adapter switching quiescent current
V_BAT = 16.8 V, V_ACDET < 0.6 V,
V_PVCC > 5 V, T_J = 85°C
V_BAT = 16.8 V, V_ACDET < 0.6 V,
V_PVCC > 5 V, T_J = 125°C
V_BAT = 16.8V, 0.6V < V_ACDET < 2.4V,
V_PVCC > 5V
Charge is disabled:
V_BAT = 16.8 V, V_ACDET > 2.4 V,
V_PVCC > 5 V
Charge is enabled:
V_BAT = 16.8 V, V_ACDET > 2.4 V,
V_PVCC > 5 V
V_PVCC = 20 V, charge disabled
V_PVCC = 20 V, Charge enabled,
converter running, total gate charge =
2 × 10 nC
7
10
µA
7
11
1
mA
3
5 mA
6
10
12 mA
2.8
4 mA
25
mA
INTERNAL SOFT START (8 steps to regulation current)
Soft start steps
8
step
Soft start step time
1.7
ms
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power-up
Delay from when adapter is detected
to when the charger is allowed to turn
on
518 700 908 ms
ISYNSET AMPLIFIER AND COMPARATOR (SYNCHRONOUS TO NON-SYSNCHRONOUS TRANSITION)
Accuracy
5 mV
–20
20 %
A_ISYNSET
Gain
ISYNSET pin voltage
ISYNSET amplifier gain
250
V/I
1
V
V_ISYNSET
ISYNSET rising deglitch
ISYNSET falling deglitch
20
µs
640
µs
LOGIC IO PIN CHARACTERISTICS (CHGEN, IADSLP )
V_{IN_LO}
Input low threshold voltage
V_{IN_HI}
Input high threshold voltage
V_BIAS
Input bias current
LOGIC INPUT PIN CHARACTERISTICS (CELLS)
V_CHGEN = 0 to V_REGN
0.8 V
2.1
1 µA
V_{IN_LO}
V_{IN_MID}
Input low threshold voltage, 3 cells
Input mid threshold voltage, 2 cells
CELLS voltage falling edge
CELLS voltage rising for MIN,
CELLS voltage falling for MAX
0.5
0.8
1.8
V
V_{IN_HI}
I_{BIAS_FLOAT}
Input high threshold voltage, 4 cells
Input bias float current for 2-cell selection
CELLS voltage rising
V
= 0 to V
2.5
–1
1 µA
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (EXTPWR)
V_{OUT_LO}
Output low saturation voltage
Delay, EXTPWR falling
Sink Current = 4 mA
0.5 V
518 700 908 ms
Delay, EXTPWR rising
10
µs
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (DPMDET, LPMD)
V_{OUT_LO}
Output low saturation voltage
Delay, rising/falling
Sink Current = 5 mA
0.5 V
10
ms
10
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