ADC084S021CIMM Datasheet, PDF (19/27 Pages) Texas Instruments – ADC084S021 4-Channel, 50 ksps to 200 Ksps, 8-Bit A/D Converter

ADC084S021
www.ti.com
SNAS279E – APRIL 2005 – REVISED MARCH 2013
The capacitor C1 in Figure 50 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor
R1 is the on resistance of the multiplexer and track / hold switch, which is typically 500 ohms. Capacitor C2 is the
ADC084S021 sampling capacitor, which is typically 30 pF. The ADC084S021 will deliver best performance when
driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance.
This is especially important when using the ADC084S021 to sample AC signals. Also important when sampling
dynamic signals is a band-pass or low-pass filter to reduce harmonics and noise, improving dynamic
performance.
VA
VIN
C1
3 pF
D1
C2
R1 ^{30 pF}
D2
Conversion Phase - Switch Open
Track Phase - Switch Closed
Figure 50. Equivalent Input Circuit
DIGITAL INPUTS AND OUTPUTS
The ADC084S021's digital output, DOUT, is limited by and cannot exceed the supply voltage, V_A. The digital
input pins are not prone to latch-up and, and although not recommended, SCLK, CS and DIN may be asserted
before V_A without any latchup risk.
POWER SUPPLY CONSIDERATIONS
The ADC084S021 is fully powered-up whenever CS is low, and fully powered-down when CS is high, with one
exception: the ADC084S021 automatically enters power-down mode between the 16th falling edge of a
conversion and the 1st falling edge of the subsequent conversion (see Timing Diagrams).
The ADC084S021 can perform multiple conversions back to back; each conversion requires 16 SCLK cycles.
The ADC084S021 will perform conversions continuously as long as CS is held low.
Power Management
When the ADC084S021 is operated continuously in normal mode, the maximum throughput is f_SCLK/16.
Performance will remain as stated in ADC084S021 Electrical Characteristics as long as the SCLK frequency
remains within the range stated at the heading of those tables. Throughput may be traded for power consumption
by running f_SCLK at its maximum 3.2 MHz and performing fewer conversions per unit time, putting the
ADC084S021 into shutdown mode between conversions. Figure 45 is shown in Typical Performance
Characteristics. To calculate the power consumption for a given throughput, multiply the fraction of time spent in
the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode
multiplied by the shutdown mode power consumption. Generally, the user will put the part into normal mode and
then put the part back into shutdown mode. Note that the curve of Figure 45 is nearly linear. This is because the
power consumption in the shutdown mode is so small that it can be ignored for all practical purposes.
Power Supply Noise Considerations
The charging of any output load capacitance requires current from the power supply, V_A. The current pulses
required from the supply to charge the output capacitance will cause voltage variations of the supply voltage. If
these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore,
discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current
into the die substrate. Load discharge currents will cause "ground bounce" noise in the substrate that will
degrade noise performance if that current is large enough. The larger is the output capacitance, the more current
flows through the die supply line and substrate, causing more noise to be coupled into the analog channel and
degrading noise performance.
Copyright © 2005–2013, Texas Instruments Incorporated
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