AM3892 Datasheet, PDF (186/299 Pages) Texas Instruments – AM389x Sitara ARM Microprocessors (MPUs)

AM3894
AM3892
SPRS681A – OCTOBER 2010 – REVISED MARCH 2011
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TCK
1
1a
1b
2
TDO
3
4
TDI/TMS
Figure 8-41. JTAG Timing
(see Figure 8-41)
NO.
1 t_c(TCK)
1a t_w(TCKH)
1b t_w(TCKL)
3 t_su(TDI-TCK)
3 t_su(TMS-TCK)
4
t_h(TCK-TDI)
t_h(TCK-TMS)
Table 8-31. Timing Requirements for IEEE 1149.1 JTAG With RTCK
Cycle time, TCK
Pulse duration, TCK high (40% of t_c)
Pulse duration, TCK low (40% of t_c)
Input setup time, TDI valid to TCK high (20% of (t_c * 0.5))
Input setup time, TMS valid to TCK high (20% of (t_c * 0.5))
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
MIN
51.15
20.46
20.46
5.115
5.115
10
10
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
Table 8-32. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
With RTCK
(see Figure 8-42)
NO.
PARAMETER
MIN
MAX UNIT
5 t_d(TCK-RTCK)
Delay time, TCK to RTCK with no selected subpaths (i.e., ICEPick
module is the only tap selected - when the ARM is in the scan
chain, the delay time is a function of the ARM functional clock.)
0
21 ns
6 t_c(RTCK)
7 t_w(RTCKH)
8 t_w(RTCKL)
Cycle time, RTCK
Pulse duration, RTCK high (40% of t_c)
Pulse duration, RTCK low (40% of t_c)
51.15
ns
20.46
ns
20.46
ns
5
TCK
6
7
8
RTCK
Figure 8-42. JTAG With RTCK Timing
186 Peripheral Information and Timings
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