TLV320AIC3256_15 Datasheet, PDF (18/52 Pages) Texas Instruments – TLV320AIC3256 Ultra Low Power Stereo Audio Codec With Embedded miniDSP

TLV320AIC3256
SLOS630C – DECEMBER 2010 – REVISED NOVEMBER 2014
8.14 DSP Timing in Slave Mode (see Figure 4)
t_H(BCLK)
t_L(BCLK)
t_s(WS)
t_h(WS)
t_d(DO-BCLK)
t_s(DI)
t_h(DI)
t_r
t_f
BCLK high period
BCLK low period
WCLK setup
WCLK hold
BCLK to DOUT delay
DIN setup
DIN hold
Rise time
Fall time
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IOVDD=1.8V
MIN MAX
35
35
8
8
22
8
8
4
4
IOVDD=3.3V
MIN MAX
35
35
8
8
22
8
8
4
4
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
WCLK
BCLK
DOUT
DIN
t_H(BCLK)
t_h(ws)
t_L(BCLK)
t_s(ws)
t_h(ws)
t_d(DO-BCLK)
t_h(ws)
t_s(DI)
Figure 4. DSP Timing in Slave Mode
t_h(DI)
18
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