THS4303 Datasheet, PDF (18/24 Pages) Texas Instruments – WIDEBAND FIXED-GAIN AMPLIFIER

THS4303
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
and may be shared among several devices in the
same area of the PC board. A very low induct-
ance path should be used to connect the in-
verting pin of the amplifier to ground. A minimum
of 5 vias as close to the part as possible is
recommended.
3. Careful selection and placement of external
components preserves the high frequency
performance of the THS4303. Resistors should
be a very low reactance type. Surface-mount
resistors work best and allow a tighter overall
layout. Axially-leaded parts do not provide good
high frequency performance, since they have ~
0.8 nH of inductance for every mm of current
path length. Again, keep PC board trace length
as short as possible. Never use wirewound type
resistors in a high frequency application. Since
the output pin and inverting input pin are the most
sensitive to parasitic capacitance, always position
the terminating resistors, if any, as close as
possible to the noninverting and output pins.
Even with a low parasitic capacitance shunting
the external resistors, excessively high resistor
values can create significant time constants that
can degrade performance. Good axial metal-film
or surface-mount resistors have approximately
0.2 pF in shunt with the resistor.
4. Connections to other wideband devices on
the board may be made with short direct
traces or through onboard transmission lines.
For short connections, consider the trace and the
input to the next device as a lumped capacitive
load. Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and set R_ISO from the
plot of recommended R_ISO vs Capacitive Load.
Low parasitic capacitive loads (<4 pF) may not
need an R_ISO since the THS4303 is nominally
compensated to operate with a 2 pF parasitic
load. Higher parasitic capacitive loads without an
R_ISO are allowed as the signal gain increases
(increasing the unloaded phase margin). If a long
trace is required, and the 6 dB signal loss
intrinsic to a doubly-terminated transmission line
is acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). With a
characteristic board trace impedance defined
based on board material and trace dimensions, a
matching series resistor into the trace from the
output of the THS4303 is used as well as a
terminating shunt resistor at the input of the
destination device. Remember also that the ter-
minating impedance is the parallel combination of
the shunt resistor and the input impedance of the
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destination device: this total effective impedance
should be set to match the trace impedance. If
the 6 dB attenuation of a doubly terminated
transmission line is unacceptable, a long trace
can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case
and set the series resistor value as shown in the
plot of R_ISO vs Capacitive Load. This does not
preserve signal integrity as well as a
doubly-terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
A 50-Ω environment is normally not necessary on
board as long as the lead lengths are short, and
in fact, a higher impedance environment im-
proves distortion as shown in the distortion ver-
sus load plots. Uncontrolled impedance traces
without double termination results in reflections at
each end, and hence, produces PCB resonances.
It is recommended that if this approach is used,
the trace length be kept short enough to avoid
resonances in the band of interest. For guidance
on useful lengths, use equation (1) given in the
Power Supply Decoupling Techniques section for
approximate resonance frequencies verses trace
length. This relation provides an upper bound on
the resonant frequency, because additional ca-
pacitive coupling to the trace from other leads or
the ground plane causes extra distributed loading
and slows the signal propagation along the trace.
5. Socketing a high-speed part like the THS4303
is not recommended. The additional lead length
inductance and pin-to-pin capacitance introduced
by the socket creates an extremely troublesome
parasitic network, which can make it almost
impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
the THS4303 onto the board.
PowerPAD™ DESIGN CONSIDERATIONS
The THS4303 is available in a thermally-enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which
the die is mounted [see Figure 48(a) and Fig-
ure 48(b)]. This arrangement results in the lead frame
being exposed as a thermal pad on the underside of
the package [see Figure 48(c)]. Because this thermal
pad has direct thermal contact with the die, excellent
thermal performance can be achieved by providing a
good thermal path away from the thermal pad.
The PowerPAD package allows both assembly and
thermal management in one manufacturing operation.
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