ADS7865 Datasheet, PDF (18/30 Pages) Texas Instruments – Dual, 12-Bit, 3+3 or 2+2 Channel, Simultaneous Sampling Analog-to-Digital Converter

ADS7865
SBAS441 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com
Sequencer Register
The ADS7865 features a programmable sequencer
that controls the switching of the ADC input
multiplexer. To set up the sequencer, two write
accesses to the ADC are required. During the first
write access, the programming of the sequencer must
be enabled by setting R[1:0] = '01' and A[2:0] = '100'
in the configuration register. The data applied to the
data bus on the second write access contain the
updated sequencer register content.
The structure of the sequencer register is shown in
Table 9. The default value of this register after
power-up is 0x000.
Detailed timing diagrams of the different sequencer
modes are shown in Figure 33.
Figure 34 shows an example where the sequencer is
set to scan through the pseudo-differential inputs of
the ADS7865 beginning with CHx1+, followed by
CHx1–, and CHx0+ while using a single CONVST
and BUSY for the entire sequence.
Table 9. Sequencer Register Map
SEQUENCER REGISTER BIT
11
10
9
8
7
6
5
4
3
2
1
0
S1
S0
SL1
SL0
CH1
CM1
CH2
CM2
CH3
CM3
SP1
SP0
Table 10. S1 and S0: Sequencer Mode
S1
S0
FUNCTION
0
X
Individual CONVST and BUSY for each conversion
1
0
Single CONVST for entire sequence and individual BUSY for each
conversion
1
1
Single CONVST and BUSY for entire sequence
Table 11. SL1 and SL0: Sequence Length
SL1
SL0
FUNCTION
0
0
Length = 0: Sequencer disabled
0
1
Length = 1: Cx1 (bits 6/7)
enabled
1
0
Length = 2: Cx1 (bits 6/7) and
Cx2 (bits 4/5) enabled
Length = 3: Cx1 (bits 6/7), Cx2
1
1
(bits 4/5), and Cx3 (bits 2/3)
enabled
CH1: Signal input of the first channel in sequence;
refer to Table 12 for details.
CM1: Common-mode input of the first channel in
sequence; refer to Table 12 for details.
CH2: Signal input of the second channel in
sequence; refer to Table 12 for details.
CM2: Common-mode input of the second channel in
sequence; refer to Table 12 for details.
CH3: Signal input of the third channel in sequence;
refer to Table 12 for details.
CM3: Common-mode input of the third channel in
sequence; refer to Table 12 for details.
Table 12. Channel Selection
CHx
0
0
1
1
CMx
0
1
0
1
ADC A/B
SIGNAL INPUT
COMMON-MODE
INPUT
CHA0+/CHB0+
CHA0–/CHB0–
CHA1–/CHB1–
CHA0–/CHB0–
CHA1+/CHB1+
CHA0–/CHB0–
CHA1+/CHB1+
CHA1–/CHB1–
Table 13. SP1 and SP0: Sequence Position
(Read-Only)
SP1
SP0
FUNCTION
0
0
Sequencer disabled
CH1/CM1 (bits 6/7) to be
0
1
converted at next falling edge
of CONVST
CH2/CM2 (bits 4/5) to be
1
0
converted at next falling edge
of CONVST
CH3/CM3 (bits 2/3) to be
1
1
converted at next falling edge
of CONVST
18
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