TSB12LV41A Datasheet, PDF (173/199 Pages) Texas Instruments – IEEE 1394-1995 Link-Layer Controller for Consumer Applications

5.101MDAltCont (MDALT @ Addr 1E0h)
This register provides the application software with the multifunction capability as defined in the functional
description. This register is cleared to 0 on power up or software reset.
BIT NUMBER BIT NAME DIR
FUNCTIONAL DESCRIPTION
00 – 31
MDALTCONT R/W^† Provides:
1. Alternate control of the packetizer when enabled with
register PKTCTL bit MDCTFRRG
2. serial cycle timer shift register when enabled with
register PKTCTL bit CYCTSEREN
3. Delayed bulky Isochronous transmit enable. When
enabled with register PKTCTL bits IWAITFCYC[0:1]
bulky Isochronous transmit begins when the cycle
timer matches the value held in MDALTCONT.
† _{This register is R/W only when the CYCTSERN bit = 0 in the PKCTL register (reg 1C4h).}
5.102Microprocessor Control Register (MDCTL @ Addr 1E4)
BIT NUMBER BIT NAME DIR
FUNCTIONAL DESCRIPTION
00 – 23
Not used
24 – 31
QPERCELL R/W^† QPERCELL indicates the quadlets per cell for
MPEG2/DSS packets. For MPEG2 Class 3, the default
QPERCELL = 47 (188 bytes); for DSS Class 3, the default
QPERCELL = 35 (140 bytes). This register allows the host
to change the number of quadlets per cell from the stan-
dard value used.
† _{This register is R/W only when the QPCWEN bit in the PKCTL register (reg 1C4h) i set.}
5.103Reserved (RSVD @ Addr 1e8h)
This register is reserved.
5–55