TSB12LV41A Datasheet, PDF (138/199 Pages) Texas Instruments – IEEE 1394-1995 Link-Layer Controller for Consumer Applications

5.13 Phy Access Register (PHYAR @ Addr 34h)
This register provides the application software with an interface for accessing the registers in the Phy.
Unless otherwise specified, this register is cleared to 0 on power up or software initiated reset. The
functionality of the register is defined by the following bit map.
BIT NUMBER
BIT NAME
DIR
FUNCTIONAL DESCRIPTION
00
RDPHYREQ
R/W Read Phy register request. When this bit is set to 1,
Phy register read request is issued from the address
specified PHYREGADR. This bit is cleared after the
link has sent the request to the Phy.
01
WRPHYREQ
R/W Write Phy register request. When this bit is set to 1, a
Phy register write request is issued to Phy that
contains the register address and write data obtained
from PHYREGADR and PHYREGWRDATA. This
request bit is cleared after the link has sent the request
to the Phy.
02 – 03
Not used
04 – 07
PHYREGADR
R/W Phy register address. This field specifies the address
of the Phy register that is read from or written to.
08 – 15
PHYREGWRDATA
R/W Phy register write data. This field specifies the data
that is written to the Phy register specified by PHYRE-
GADR.
16 – 19
Not used
20 – 23
PHYREGADRRCV
R Phy register address received. These register bits
buffer the register address returned by the Phy in
response to a Phy register read request. The host
processor can write to these bits when the REGRW bit
in diagnostic control register (DIAG @ Addr 30h) is set
to 1.
24 – 31
PHYREGDATARCV R Phy register data received. These register bits buffer
the data returned by the Phy in response to a Phy
register read request. The host processor can write to
these bits when the REGRW bit in diagnostic control
register (DIAG @ Addr 30h) is set to 1.
5–20