TMS320DM368_101 Datasheet, PDF (170/208 Pages) Texas Instruments – TMS320DM368 Digital Media System-on-chip(DMSoC)

TMS320DM368
SPRS668A – APRIL 2010
www.ti.com
Table 6-70. Switching Characteristics for I2C Timings⁽¹⁾ (see Figure 6-48)
DEVICE
NO.
PARAMETER
STANDARD
MODE
FAST MODE
MIN MAX MIN MAX
16
t_c(SCL)
Cycle time, SCL
10
2.5
17
t_d(SCLH-SDAL)
Delay time, SCL high to SDA low (for a repeated START condition)
4.7
0.6
18
t_d(SDAL-SCLL)
Delay time, SDA low to SCL low (for a START and a repeated
START condition)
4
0.6
19
t_w(SCLL)
20
t_w(SCLH)
21
t_d(SDAV-SCLH)
22
t_v(SCLL-SDAV)
23
t_w(SDAH)
28
t_d(SCLH-SDAH)
29
C_p
Pulse duration, SCL low
Pulse duration, SCL high
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low (For I2C devices)
Pulse duration, SDA high between STOP and START conditions
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I2C pin
4.7
1.3
4
0.6
250
100
0
0 0.9
4.7
1.3
4
0.6
10
10
(1) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
UNIT
ms
ms
ms
ms
ms
ns
ms
ms
ms
pF
CAUTION
The I²C pins use a standard ±4-mA LVCMOS buffer, not the slow I/OP buffer defined in
the I²C specification. Series resistors may be necessary to reduce noise at the system
level.
SDA
SCL
Stop
23
19
21
20
Start
16
18
18
22
17
Repeated
Start
Figure 6-48. I2C Transmit Timings
28
Stop
170 Peripheral Information and Electrical Specifications
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