TPS40132_15 Datasheet, PDF (17/42 Pages) Texas Instruments – TWO-PHASE, SYNCHRONOUS BUCK CONTROLLER WITH INTEGRATED MOSFET DRIVERS

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TPS40132
SLUS776B – DECEMBER 2007 – REVISED JUNE 2011
LAYOUT CONSIDERATIONS
Power Stage
A synchronous BUCK power stage has two primary current loops. One is the input current loop that carries high
AC discontinuous current . The other is the output current loop that carries high DC continuous current.
The input current loop includes the input capacitors, the main switching MOSFET, the inductor, the output
capacitors and the ground path back to the input capacitors. To keep this loop as small as possible, it is
generally good practice to place some ceramic capacitance directly between the drain of the main switching
MOSFET and the source of the synchronous rectifier (SR) through a power ground plane directly under the
MOSFETs.
The output current loop includes the SR MOSFET, the inductor, the output capacitors, and the ground return
between the output capacitors and the source of the SR MOSFET. As with the input current loop, the ground
return between the output capacitor ground and the source of the SR MOSFET should be routed under the
inductor and SR MOSFET to minimize the power loop area.
The SW node area should be as small as possible to reduce the parasitic capacitance and minimize the radiated
emissions. The gate drive loop impedance (HDRV-gate-source-SW and LDRV-gate-source- GND) should be
kept to as low as possible. The HDRV and LDRV connections should widen to 20 mils as soon as possible out
from the device's pin.
Device Peripheral
The TPS40132 provides separate signal ground (GND) and power ground (PGND) pins. It is required to separate
properly the circuit grounds. The return path for the pins associated with the power stage should be through
PGND. The other pins especially for those sensitive pins such as FB, RT and ILIM should be through the low
noise GND. The GND and PGND plane are suggested to be connected at the output capacitor with single 20 mil
trace.
A minimum 0.1-μF ceramic capacitor must be placed as close to the VDD pin and GND as possible with at least
15-mil wide trace from the bypass capacitor to the GND. A 1-μF ceramic capacitor should be placed as close to
VIN5 pin and GND as possible.
BP5 is the filtered input from the VIN5 pin. A 10 Ω resistor should be connected between VIN5 and BP5 and a
1-μF ceramic capacitor should be connected from BP5 to GND. Both components should be as close to BP5 pin
as possible.
When DCR sensing method is applied, the sensing resistor is placed close to the SW node. It is connected to the
inductor with Kelvin connection. The sensing traces from the power stage to the device should be away from the
switching components. The sensing capacitor should be placed very close to the CS and CSRT pins. The
frequency setting resistor should be placed as close to RT pin and GND as possible.
The VOUT and GSNS pins should be directly connected to the point of load where the voltage regulation is
required. A parallel pair of 10-mil traces connects the regulated voltage back to the chip. They should be away
from the switching components. The PowerPAD™ should be electrically connected to GND. Figure 7 shows the
device peripheral schematic and Figure 8 shows the suggested layout.
The resistance value of R7 in Figure 7 and Figure 8 can be zero. R7 provides more flexibility for loop gain
measurement by using a low resistance value.
Copyright © 2007–2011, Texas Instruments Incorporated
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