THS4302 Datasheet, PDF (17/23 Pages) Texas Instruments – WIDEBAND FIXED-GAIN AMPLIFIER

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nH of inductance for every mm of current path
length. Again, keep PC board trace length as
short as possible. Never use wirewound type
resistors in a high frequency application. Because
the output pin and inverting input pin are the most
sensitive to parasitic capacitance, always position
the terminating resistors, if any, as close as
possible to the noninverting and output pins.
Even with a low parasitic capacitance shunting
the external resistors, excessively high resistor
values can create significant time constants that
can degrade performance. Good axial metal-film
or surface-mount resistors have approximately
0.2 pF in shunt with the resistor.
4. Connections to other wideband devices on
the board may be made with short direct
traces or through onboard transmission lines.
For short connections, consider the trace and the
input to the next device as a lumped capacitive
load. Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and set R_ISO from the
plot of recommended R_ISO vs Capacitive Load.
Low parasitic capacitive loads (<4 pF) may not
need an R_ISO because THS4302 amplifiers are
nominally compensated to operate with a 2-pF
parasitic load. Higher parasitic capacitive loads
without an R_ISO are allowed as the signal gain
increases (increasing the unloaded phase mar-
gin). If a long trace is required, and the 6-dB
signal loss intrinsic to a doubly-terminated trans-
mission line is acceptable, implement a matched
impedance transmission line using microstrip or
stripline techniques (consult an ECL design hand-
book for microstrip and stripline layout tech-
niques). With a characteristic board trace im-
pedance defined based on board material and
trace dimensions, a matching series resistor into
the trace from the output of the THS4302 is used
as well as a terminating shunt resistor at the input
of the destination device. Remember also that the
terminating impedance is the parallel combination
of the shunt resistor and the input impedance of
the destination device: this total effective im-
pedance should be set to match the trace im-
pedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a
long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in
this case, and set the series resistor value as
shown in the plot of R_ISO vs Capacitive Load. This
does not preserve signal integrity as well as a
doubly terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
THS4302
SLOS403G – OCTOBER 2002 – REVISED JANUARY 2005
A 50-Ω environment is normally not necessary on
board as long as the lead lengths are short, and
in fact, a higher impedance environment im-
proves distortion as shown in the distortion ver-
sus load plots. Uncontrolled impedance traces
without double termination results in reflections at
each end, and hence, produces PCB resonances.
It is recommended that if this approach is used,
the trace length be kept short enough to avoid
resonances in the band of interest. For guidance
on useful lengths, use equation (1) given in the
Power Supply Decoupling Techniques section for
approximate resonance frequencies vs trace
length. This relation provides an upper bound on
the resonant frequency, because additional ca-
pacitive coupling to the trace from other leads or
the ground plane causes extra distributed loading
and slows the signal propagation along the trace.
5. Socketing a high-speed part like the THS4302
is not recommended. The additional lead length
inductance and pin-to-pin capacitance introduced
by the socket creates an extremely troublesome
parasitic network, which can make it almost
impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
the THS4302 onto the board.
PowerPAD™ DESIGN CONSIDERATIONS
The THS4302 is available in a thermally enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe on which the
die is mounted [see Figure 49(a) and Figure 49(b)].
This arrangement results in the lead frame being
exposed as a thermal pad on the underside of the
package [see Figure 49(c)]. Because this thermal pad
has direct thermal contact with the die, excellent
thermal performance can be achieved by providing a
good thermal path away from the thermal pad.
The PowerPAD package allows both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also
be soldered to a copper area underneath the pack-
age. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the heretofore awkward mechan-
ical methods of heatsinking.
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