MSP430G2302-EP Datasheet, PDF (17/48 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430G2302-EP
www.ti.com
SLAS868 – JUNE 2012
Absolute Maximum Ratings⁽¹⁾
Voltage applied at V_CC to V_SS
Voltage applied to any pin⁽²⁾
Diode current at any device pin
Storage temperature range, T_stg(3)
Unprogrammed device
Programmed device
–0.3 V to 4.1 V
–0.3 V to V_CC + 0.3 V
±2 mA
–55°C to 150°C
–55°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V_SS. The JTAG fuse-blow voltage, V_FB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Information
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
THERMAL METRIC
Junction-to-ambient thermal resistance⁽¹⁾
Junction-to-case (top) thermal resistance⁽²⁾
Junction-to-board thermal resistance⁽³⁾
Junction-to-top characterization parameter⁽⁴⁾
Junction-to-board characterization parameter⁽⁵⁾
Junction-to-case (bottom) thermal resistance⁽⁶⁾
MSP430G2302
PW
14 PINS
98.7
26.8
41.2
1.1
40.5
N/A
UNITS
°C/W
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2012, Texas Instruments Incorporated
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