OMAP-L138_0908 Datasheet, PDF (162/268 Pages) Texas Instruments – OMAP-L138 Low-Power Applications Processor

OMAP-L138 Low-Power Applications Processor
SPRS586A – JUNE 2009 – REVISED AUGUST 2009
www.ti.com
Table 6-68. Additional SPI0 Slave Timings, 5-Pin Option ^(1)(2)(3)
NO.
25 t_{d(SCSL_SPC)S}
26 t_{d(SPC_SCSH)S}
27 t_{ena(SCSL_SOMI)S}
28 t_{dis(SCSH_SOMI)S}
29 t_{ena(SCSL_ENA)S}
30 t_{dis(SPC_ENA)S}
PARAMETER
Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Required delay from final SPI0_CLK edge before SPI0_SCS is
deasserted.
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid
Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI
Delay from master deasserting SPI0_SCS to slave driving SPI0_ENA valid
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Delay from final clock receive edge on SPI0_CLK to slave 3-stating
or driving high SPI0_ENA.⁽⁴⁾
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
1.2V
MIN
MAX
P + 1.5
0.5M+P
+4
1.1V
MIN
MAX
P + 1.5
0.5M+P
+4
1.0V
MIN
MAX
P + 1.5
0.5M+P
+5
UNIT
ns
P+4
P+4
P+5
ns
0.5M+P
0.5M+P
0.5M+P
+4
+4
+5
P+4
P+4
P+5
P+17.5
P+17.5
17.5
2.5P+17
.5
2.5P+17
.5
2.5P+17
.5
2.5P+17
.5
P+20
P+20
20
2.5P+20
2.5P+20
2.5P+20
2.5P+20
P+27 ns
P+27 ns
27
ns
2.5P+27
2.5P+27
ns
2.5P+27
2.5P+27
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-62).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor
should be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.
162 Peripheral Information and Electrical Specifications
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