OMAP-L138_0908 Datasheet, PDF (143/268 Pages) Texas Instruments – OMAP-L138 Low-Power Applications Processor

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OMAP-L138 Low-Power Applications Processor
SPRS586A – JUNE 2009 – REVISED AUGUST 2009
Table 6-52. Switching Characteristics for McBSP0 [1.2V, 1.1V]⁽¹⁾⁽²⁾
(see Figure 6-33)
NO.
PARAMETER
1.2V
MIN
MAX
1.1V
MIN
MAX
UNIT
1
t_{d(CKSH-CKRXH)}
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
2
14.5
2
16
ns
2 t_c(CKRX)
Cycle time, CLKR/X
CLKR/X int
2P or
20 ^{(3) (4) (5)}
2P or
25^{(3) (4) (5)}
ns
3 t_w(CKRX)
Pulse duration, CLKR/X high or
CLKR/X low
CLKR/X int
C - 2⁽⁶⁾
C + 2⁽⁶⁾
C - 2⁽⁶⁾
C + 2⁽⁶⁾
ns
4 t_d(CKRH-FRV)
Delay time, CLKR high to internal FSR ^{CLKR int}
valid
CLKR ext
-4
2
5.5
14.5
-4
2
5.5
ns
16
9 t_d(CKXH-FXV)
Delay time, CLKX high to internal FSX ^{CLKX int}
valid
CLKX ext
-4
2
5.5
14.5
-4
2
5.5
ns
16
12
t_{dis(CKXH-DXHZ)}
Disable time, DX high impedance
following last data bit from CLKX high
13 t_d(CKXH-DXV)
14 t_d(FXH-DXV)
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
FSX ext
-4
7.5
-5.5
7.5
ns
-2
16
-22
16
-4 + D1⁽⁷⁾ 5.5 + D2⁽⁷⁾ -4 + D1⁽⁷⁾ 5.5 + D2⁽⁷⁾
2 + D1⁽⁷⁾ 14.5 + D2⁽⁷⁾ 2 + D1⁽⁷⁾
16 + D2⁽⁷⁾
ns
-4 ⁽⁸⁾
5 ⁽⁸⁾
-4 ⁽⁸⁾
5 ⁽⁸⁾
-2 ⁽⁸⁾
14.5 ⁽⁸⁾
-2 ⁽⁸⁾
16 ⁽⁸⁾
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(4) P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(5) Use whichever value is greater.
(6) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
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Peripheral Information and Electrical Specifications 143