TPS54560_15 Datasheet, PDF (16/46 Pages) Texas Instruments – TPS54560 4.5 V to 60 V Input, 5 A, Step Down DC-DC Converter with Eco-mode

TPS54560
SLVSBN0A – MARCH 2013 – REVISED MARCH 2014
www.ti.com
Feature Description (continued)
f_{SW(max skip)}
=
1
t_ON
æ
´
ç
çè
I_O ´ R_dc + V_OUT + V_d
V_IN - I_O ´ R_DS(on) + V_d
ö
÷
÷ø
(8)
f_SW(shift) =
f_DIV
t_ON
´
æ
ç
çè
I_CL ´ R_dc + V_OUT(sc) + V_d
V_IN - I_CL ´ R_DS(on) + V_d
ö
÷
÷ø
(9)
I_O Output current
I_CL Current limit
Rdc inductor resistance
V_IN maximum input voltage
V_OUT output voltage
V_OUTSC output voltage during short
Vd diode voltage drop
R_DS(on) switch on resistance
t_ON controllable on time
ƒ_DIV frequency divide equals (1, 2, 4, or 8)
8.3.11 Synchronization to RT/CLK Terminal
The RT/CLK terminal can receive a frequency synchronization signal from an external system clock. To
implement this synchronization feature connect a square wave to the RT/CLK terminal through either circuit
network shown in Figure 27. The square wave applied to the RT/CLK terminal must switch lower than 0.5 V and
higher than 1.7 V and have a pulsewidth greater than 15 ns. The synchronization frequency range is 160 kHz to
2300 kHz. The rising edge of the SW will be synchronized to the falling edge of RT/CLK terminal signal. The
external synchronization circuit should be designed such that the default frequency set resistor is connected from
the RT/CLK terminal to ground when the synchronization signal is off. When using a low impedance signal
source, the frequency set resistor is connected in parallel with an ac coupling capacitor to a termination resistor
(e.g., 50 Ω) as shown in Figure 27. The two resistors in series provide the default frequency setting resistance
when the signal source is turned off. The sum of the resistance should set the switching frequency close to the
external CLK frequency. It is recommended to ac couple the synchronization signal through a 10 pF ceramic
capacitor to RT/CLK terminal.
The first time the RT/CLK is pulled above the PLL threshold the TPS54560 switches from the RT resistor free-
running frequency mode to the PLL synchronized mode. The internal 0.5 V voltage source is removed and the
RT/CLK terminal becomes high impedance as the PLL starts to lock onto the external signal. The switching
frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from
the resistor mode to the PLL mode and locks onto the external clock frequency within 78 microseconds. During
the transition from the PLL mode to the resistor programmed mode, the switching frequency will fall to 150 kHz
and then increase or decrease to the resistor programmed frequency when the 0.5 V bias voltage is reapplied to
the RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB terminal voltage ramps from 0 to 0.8 volts. The
device implements a digital frequency foldback to enable synchronizing to an external clock during normal start-
up and fault conditions. Figure 28, Figure 29 and Figure 30 show the device synchronized to an external system
clock in continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).
SPACER
16
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