TMS626812B Datasheet, PDF (16/40 Pages) Texas Instruments – 1,048,576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES

electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted)
(see Note 6)
PARAMETER
TEST CONDITIONS
’626812B-8 ’626812B-8A
MIN MAX MIN MAX
VOH
VOL
II
IO
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
High-level output voltage
Low-level output voltage
Input current (leakage)
Output current (leakage)
Operating current
Precharge standby current
in power-down mode
Precharge standby current
in non-power-down mode
Active standby current in
power-down mode
Active standby current in
non-power-down mode
IOH = –4 mA
IOL = 4 mA
0 V ≤ VI ≤ VCC + 0.3 V,
All other pins = 0 V to VCC
0 V ≤ VO ≤ VCC + 0.3 V,
Output disabled
w Burst length = 1, tRC tRC MIN
CAS latency = 2
IOH/IOL = 0 mA, 1 bank activated
(see Notes 7, 8, and 9)
CAS latency = 3
v CKE VIL MAX, tCK = 15 ns (see Note 10)
v CKE and CLK VIL MAX, tCK = ∞ (see Note 11)
w CKE VIH MIN, tCK = 15 ns (see Note 10)
w v CKE VIH MIN, CLK VIL MAX, tCK = ∞ (see Note 11)
v CKE VIL MAX, tCK = 15 ns (see Notes 7 and 10)
v CKE and CLK VIL MAX, tCK = ∞ (see Notes 7 and 11)
w CKE VIH MIN, tCK = 15 ns (see Notes 7 and 10)
w v CKE VIH MIN, CLK VIL MAX, tCK = ∞ (see Notes 7 and 11)
2.4
0.4
±10
±10
95
100
1
1
30
2
3
3
40
10
2.4
0.4
±10
±10
95
100
1
1
30
2
3
3
40
10
ICC4
Burst current
Page burst, IOH/IOL = 0 mA
All banks activated, nCCD = 1 cycle
(see Notes 12 and 13)
CAS latency = 2
CAS latency = 3
140
140
150
150
ICC5
ICC6
Auto-refresh current
Self-refresh current
v tRC tRC MIN (see Note 11)
v CKE VIL MAX
CAS latency = 2
CAS latency = 3
90
95
0.400
NOTES: 6. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
7. Only one bank is activated.
8. tRC = MIN
9. Control, DQ, and address inputs change state only twice during tRC.
10. Control, DQ, and address inputs change state only once every 30 ns.
11. Control, DQ, and address inputs do not change (stable).
12. Control, DQ, and address inputs change state only once every cycle.
13. Continuous burst access, nCCD = 1 cycle.
90
95
0.400
’626812B-10
MIN MAX
2.4
0.4
±10
±10
85
90
1
1
30
2
3
3
40
10
130
140
80
85
0.400
UNIT
V
V
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA