THS1060 Datasheet, PDF (16/21 Pages) Texas Instruments – 10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER

THS1060
10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS212 – MARCH 2000
APPLICATION INFORMATION
3 V – 5 V p-p
Impedance Ratio = 1:4
0.1 µF
Zo
CLK+
T4-1H
4 Zo ^THS1060
CLK–
VCM
0.01 µF
0.1 µF
Figure 21. Coaxial Clock Source
The clock signals, CLK+ and CLK– should be well matched and must both be driven.
A transformer ensures minimal skew between the two complementary channels. However, skew levels of up
to 500 ps between CLK+ and CLK– can be tolerated with some performance degradation.
The clock input can also be driven differentially with a 5 V TTL signal by using an RF transformer to convert the
TTL signal to a differential signal. The TTL signal is ac coupled to the positive primary terminal with a high pass
circuit. The negative terminal of the transformer is connected to ground (see Figure 22). The transformer
secondary is connected to the CLK inputs.
5 V TTL CLK
Impedance Ratio = 1:4
0.1 µF
CLK+
T4 - 1H
THS1060
CLK–
VCM
0.01 µF
Figure 22. TTL Clock Input
0.1 µF
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