TAS5176 Datasheet, PDF (16/25 Pages) Texas Instruments – 6-Channel, 100-W, Digital-Amplifier Power Stage

TAS5176
SLES196 – JUNE 2007
www.ti.com
THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5176 needs only
a 12-V supply in addition to a typical 31-V
power-stage supply. An internal voltage regulator
provides suitable voltage levels for the digital and
low-voltage analog circuitry. Additionally, all circuitry
requiring a floating voltage supply, e.g., the high-side
gate drive, is accommodated by built-in bootstrap
circuitry requiring only a few external capacitors.
In order to provide outstanding electrical and
acoustic characteristics, the PWM signal path
including gate drive and output stage is designed as
identical, independent half-bridges. For this reason,
each half-bridge has separate bootstrap pins
(BST_X) and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as
power supply for all common circuits. Although
supplied from the same 12-V source, it is highly
recommended to separate GVDD_X and VDD on the
printed-circuit board (PCB) by RC filters (see
application diagram for details). These RC filters
provide the recommended high-frequency isolation.
Special attention should be paid to placing all
decoupling capacitors as close to their associated
pins as possible. In general, inductance between the
power-supply pins and decoupling capacitors must
be avoided. (See reference board documentation for
additional information.)
For a properly functioning bootstrap circuit, a small
ceramic capacitor must be connected from each
bootstrap pin (BST_X) to the power-stage output pin
(OUT_X). When the power-stage output is low, the
bootstrap capacitor is charged through an internal
diode connected between the gate-drive
power-supply pin (GVDD_X) and the bootstrap pin.
When the power-stage output voltage is high, the
bootstrap capacitor voltage is shifted above the
output voltage potential and thus provides a suitable
voltage supply for the high-side gate driver. In an
application with PWM switching frequencies in the
range 352 kHz to 384 kHz, it is recommended to use
33-nF ceramic capacitors, size 0603 or 0805, for the
bootstrap capacitor. These 33-nF capacitors ensure
sufficient energy storage, even during minimal PWM
duty cycles, to keep the high-side power stage FET
(LDMOS) fully started during all of the remaining part
of the PWM cycle. In an application running at a
reduced switching frequency, generally 250 kHz to
192 kHz, the bootstrap capacitor might need to be
increased in value. Special attention should be paid
to the power-stage power supply; this includes
component selection, PCB placement and routing.
As indicated, each half-bridge has independent
power-stage supply pins (PVDD_X). For optimal
electrical performance, EMI compliance, and system
reliability it is important that each PVDD_X pin is
decoupled with a 100-nF ceramic capacitor placed
as close as possible to each supply pin on the same
side of the PCB as the TAS5176. It is recommended
to follow the PCB layout and PowerPad layout of the
TAS5176 reference design. For additional
information on the recommended power supply and
required components, see the application diagrams
given in this data sheet. The 12-V supply should be
powered from a low-noise, low-output-impedance
voltage regulator. Likewise, the PVDD power-stage
supply is assumed to have low output impedance
and low noise. The power-supply sequence is not
critical due to the internal power-on-reset circuit.
Moreover, the TAS5176 is fully protected against
erroneous power-stage turnon due to parasitic gate
charging. Thus, voltage-supply ramp rates (dv/dt) are
typically noncritical.
SYSTEM POWER-UP/DOWN SEQUENCE
The TAS5176 does not require a power-up
sequence. The outputs of the H-bridge remain in a
high-impedance state until the gate-drive supply
voltage (GVDD_X) and VDD voltage are above the
undervoltage protection (UVP) voltage threshold (see
the Electrical Characteristics section of this data
sheet). Although not specifically required, it is
recommended to hold RESET in a low state while
powering up the device.
When the TAS5176 is being used with TI PWM
modulators such as the TAS5086, no special
attention to the state of RESET is required, provided
that the chipset is configured as recommended.
Powering Down
The TAS5176 does not require a power-down
sequence. The device remains fully operational as
long as the gate-drive supply (GVDD_X) voltage and
VDD voltage are above the undervoltage protection
(UVP) threshold level (see the Electrical
Characteristics section of this data sheet). Although
not specifically required, it is a good practice to hold
RESET low during power down, thus preventing
audible artifacts including pops and clicks
When the TAS5176 is being used with TI PWM
modulators such as the TAS5086, no special
attention to the state of RESET is required, provided
that the chipset is configured as recommended.
Error Reporting
The SD and OTW pins are both active-low,
open-drain outputs. Their function is for
protection-mode signaling to a PWM controller or
other system-control device.
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