OPA3692IDBQT Datasheet, PDF (16/27 Pages) Texas Instruments – Triple, Wideband, Fixed Gain Video BUFFER AMPLIFIER With Disable

DISABLE OPERATION
The OPA3692 provides an optional disable feature that can
be used either to reduce system power or to implement a
simple channel multiplexing operation. If the DIS control pin
is left unconnected, the OPA3692 operates normally. To
disable, the control pin must be asserted LOW. Figure 8
shows a simplified internal circuit for the disable control
feature.
+V_S
15kΩ
Q1
V_DIS
25kΩ
I_S
Control
110kΩ
–V_S
FIGURE 8. Simplified Disable Control Circuit.
In normal operation, base current to Q1 is provided through the
110kΩ resistor while the emitter current through the 15kΩ
resistor sets up a voltage drop that is inadequate to turn on the
two diodes in the Q1 emitter. As V_DIS is pulled LOW, additional
current is pulled through the 15kΩ resistor, eventually turning
on these two diodes (≈ 75µA). At this point, any additional
current pulled out of V_DIS goes through those diodes holding
the emitter-base voltage of Q1 at approximately 0V. This shuts
off the collector current out of Q1, turning the amplifier off. The
supply current in the disable mode is only what is required to
operate the circuit of Figure 8. Additional circuitry ensures that
turn-on time occurs faster than turn-off time (make-before-
break).
When disabled, the output and input nodes go to a high-
impedance state. If the OPA3692 is operating in a gain of +1,
this shows a very high impedance (2pF || 1MΩ) at the output
and exceptional signal isolation. If operating at a gain of +2, the
total feedback network resistance (R_F + R_G) will appear as the
impedance looking back into the output, but the circuit will still
show very high forward and reverse isolation. If configured as
an inverting amplifier, the input and output will be connected
through the feedback network resistance (R_F + R_G) giving
relatively poor input to output isolation.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Typical
Characteristics show these glitches for the circuit of Figure 1
with the input signal set to 0V. The glitch waveform at the
output pin is plotted along with the DIS pin voltage.
The transition edge rate (dV/dt) of the DIS control line
influences this glitch. For the curve, Disable/Enable Glitch,
shown in the Typical Characteristics, the edge rate was
reduced until no further reduction in glitch amplitude was
observed. This approximately 1V/ns maximum slew rate can
be achieved by adding a simple RC filter into the V_DIS pin
from a higher speed logic line. If extremely fast transition
logic is used, a 2kΩ series resistor between the logic gate
and the DIS input pin provides adequate bandlimiting using
just the parasitic input capacitance on the DIS pin while still
ensuring an adequate logic level swing.
THERMAL ANALYSIS
Due to the high output power capability of the OPA3692,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature
will set the maximum allowed internal power dissipation as
described following. In no case should the maximum junction
temperature be allowed to exceed 175°C.
Operating junction temperature (T_J) is given by T_A + P_D • θ_JA.
The total internal power dissipation (P_D) is the sum of quies-
cent power (P_DQ) and additional power dissipated in the output
stage (P_DL) to deliver load power. Quiescent power is simply
the specified no-load supply current times the total supply
voltage across the part. P_DL depends on the required output
signal and load but, for a grounded resistive load, be at a
maximum when the output is fixed at a voltage equal to
1/2 of either supply voltage (for equal bipolar supplies). Under
this condition P_DL = V_S2/(4 • R_L), where R_L includes feedback
network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T_J using an
OPA3692 in the circuit of Figure 1 operating at the maximum
specified ambient temperature of +85°C with all three outputs
driving a grounded 100Ω load to +2.5V:
P_D = 10V • 17.4mA + 3 (5²/(4 • (100Ω || 804Ω)) = 384mW
Maximum T_J = +85°C + (0.384W • 100°C/W) = 123.4°C
This worst-case condition is within the maximum junction
temperature. Normally, this extreme case is not encountered.
Careful attention to internal power dissipation is required.
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OPA3692
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