MSP430C13X1 Datasheet, PDF (16/35 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430C13x1
MIXED SIGNAL MICROCONTROLLER
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
VIT+
Positive-going input threshold voltage
VIT−
Negative-going input threshold voltage
Vhys Input voltage hysteresis (VIT+ − VIT−)
TEST CONDITIONS
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
MIN TYP MAX UNIT
1.1
1.5
V
1.5
1.9
0.4
0.9
V
0.90
1.3
0.3
1.1
V
0.4
1
standard inputs − RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
TEST CONDITIONS
MIN
VIL Low-level input voltage
VIH High-level input voltage
VCC = 2.2 V / 3 V
VSS
0.8×VCC
TYP
MAX
VSS+0.6
VCC
UNIT
V
V
input frequency − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
f(IN)
t(h) = t(L)
VCC = 2.2 V
VCC = 3 V
MIN TYP MAX UNIT
8
MHz
10
capture timing _ Timer_A3: TA0, TA1, TA2; Timer_B3: TB0, TB1, TB2
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT
Ports P2, P4:
t(int) _{External trigger signal for the interrupt flag (see Notes 1 and 2)}
VCC = 2.2 V/3 V
1.5
VCC = 2.2 V
62
VCC = 3 V
50
Cycle
ns
NOTES: 1. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int).
The conditions to set the flag must be met independently of this timing constraint. t(int) is defined in MCLK cycles.
2. The external signal needs additional timing because of the maximum input-frequency constraint.
external interrupt timing
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT
Ports P1, P2:
t(int) _{External trigger signal for the interrupt flag (see Notes 1 and 2)}
VCC = 2.2 V/3 V
1.5
VCC = 2.2 V
62
VCC = 3 V
50
Cycle
ns
NOTES: 1. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int).
The conditions to set the flag must be met independently of this timing constraint. t(int) is defined in MCLK cycles.
2. The external signal needs additional timing because of the maximum input-frequency constraint.
leakage current (see Note 1)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
Ilkg(P1.x)
Ilkg(P2.x)
Leakage
current
Port P1 V(P1.x) (see Note 2)
Port P2 V(P2.3) V(P2.4) (see Note 2)
VCC = 2.2 V/3 V
±50
±50
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.
UNIT
nA
16
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265