DAC8832 Datasheet, PDF (16/26 Pages) Texas Instruments – 16-Bit, Ultra-Low Power, Voltage-Output Digital-to-Analog Converter

DAC8832
SBAS380A – FEBRUARY 2006 – REVISED APRIL 2006
www.ti.com
THEORY OF OPERATION (continued)
POWER-ON RESET
The DAC8832 has a power-on reset function to ensure the output is at a known state upon power-up. Upon
power-up, the DAC latch and input register contain mid-scale code until new data is loaded from the input serial
shift register. Therefore, after power-up, the output from pin V_OUT is 0.5 × V_REF in unipolar mode, and 0V in
bipolar mode.
However, the serial register is not cleared on power-up, so its contents are undefined. When loading data initially
to the device, 16 bits or more should be loaded to prevent erroneous data appearing on the output. If more than
16 bits are loaded, the last 16 are kept; if less than 16 are loaded, bits will remain from the previous word. If the
device must be interfaced with data shorter than 16 bits, the data should be padded with 0s at the LSBs.
SERIAL INTERFACE
The digital interface is standard 3-wire connection compatible with SPI, QSPI™, Microwire™, and TI DSP
interfaces, which can operate at speeds up to 50M-bits/sec. The data transfer is framed by CS, the chip select
signal. The DAC works as a bus slave. The bus master generates the synchronize clock, SCLK, and initiates the
transmission. When CS is high, the DAC is not accessed, and the clock SCLK and serial input data SDI are
ignored. The bus master accesses the DAC by driving pin CS low. Immediately following the high-to-low
transition of CS, the serial input data on pin SDI is shifted out from the bus master synchronously on the falling
edge of SCLK, and latched on the rising edge of SCLK into the input shift register, MSB first. The low-to-high
transition of CS transfers the contents of the input shift register to the input register. All data registers are 16-bit.
It takes 16 clocks of SCLK to transfer one data word to the parts. To complete a whole data word, CS must go
high immediately after 16 SCLKs are clocked in. If more than 16 SCLKs are applied during the low state of CS,
the last 16 bits are transferred to the input register on the rising edge of CS. However, if CS is not kept low
during the entire 16 SCLK cycles, data is corrupted. In this case, reload the DAC with a new 16-bit word.
The DAC8832 has an LDAC pin allowing the DAC latch to be updated asynchronously by bringing LDAC low
after CS goes high. In this case, LDAC must be maintained high while CS is low. If LDAC is tied permanently
low, the DAC latch is updated immediately after the input register is loaded (caused by the low-to-high transition
of CS).
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