SM320F28335-HT Datasheet, PDF (150/158 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-HT
SPRS682 – DECEMBER 2010
www.ti.com
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by
setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will
be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
CLKX
FSX
DX
DR
LSB
M32
MSB
M33
M24
M25
M28
M29
Bit 0
Bit 0
Bit(n-1)
(n-2)
M30
M31
(n-3)
(n-4)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-38. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)⁽¹⁾
NO.
M39 t_su(DRV-CKXH)
Setup time, DR valid before CLKX high
M40 t_h(CKXH-DRV)
Hold time, DR valid after CLKX high
M41 t_su(FXL-CKXH)
Setup time, FSX low before CLKX high
M42 t_c(CKX)
Cycle time, CLKX
(1) Not production tested.
(2) 2P = 1/CLKG
MASTER
SLAVE
MIN
MAX
MIN MAX
30
8P – 10
1
8P – 10
2P ⁽²⁾
16P + 10
16P
UNIT
ns
ns
ns
ns
Table 6-59. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)⁽¹⁾
NO.
PARAMETER
M34
M35
M37
t_h(CKXL-FXL)
t_d(FXL-CKXH)
t_{dis(CKXL-DXHZ)}
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
Disable time, DX high impedance following last data bit
from CLKX low
M38
t_d(FXL-DXV)
Delay time, FSX low to DX valid
(1) Not production tested.
(2) 2P = 1/CLKG
MASTER
MIN
MAX
P
2P ⁽²⁾
P+6
SLAVE
MIN MAX
7P + 6
UNIT
ns
ns
ns
6
4P + 6
ns
150 Electrical Specifications
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