SM320F28335-HT Datasheet, PDF (121/158 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-HT
www.ti.com
SPRS682 – DECEMBER 2010
Table 6-32. SPI Master Mode External Timing (Clock Phase = 1)^{(1) (2) (3) (4) (5)(6)}
NO.
SPI WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0
OR 2
MIN
MAX
1 t_c(SPC)M
2 t_w(SPCH)M
Cycle time, SPICLK
Pulse duration, SPICLK high
(clock polarity = 0)
4t_c(LCO)
0.5t_c(SPC)M -10
128t_c(LCO)
0.5t_c(SPC)M
t_w(SPCL))M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5t_c(SPC)M -10
0.5t_c(SPC)M
3 t_w(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5t_c(SPC)M -10
0.5t_c(SPC)M
t_w(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5t_c(SPC)M -10
0.5t_c(SPC)M
6 t_{su(SIMO-SPCH)M}
Setup time, SPISIMO data valid before
SPICLK high (clock polarity = 0)
0.5t_c(SPC)M -10
t_{su(SIMO-SPCL)M}
Setup time, SPISIMO data valid before
SPICLK low (clock polarity = 1)
0.5t_c(SPC)M -10
7 t_{v(SPCH-SIMO)M}
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
0.5t_c(SPC)M -10
t_{v(SPCL-SIMO)M}
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
0.5t_c(SPC)M -10
10 t_{su(SOMI-SPCH)M}
Setup time, SPISOMI before SPICLK high
35
(clock polarity = 0)
t_{su(SOMI-SPCL)M}
Setup time, SPISOMI before SPICLK low
35
(clock polarity = 1)
11 t_{v(SPCH-SOMI)M}
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
0.25t_c(SPC)M -10
t_{v(SPCL-SOMI)M}
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
0.25_tc(SPC)M -10
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) t_c(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5 MHz MAX.
(4) t_c(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
(6) Not production tested.
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
MIN
5t_c(LCO)
0.5t_c(SPC)M - 0.5t_{c (LCO)}-
10
0.5t_c(SPC)M - 0.5t_{c (LCO)}-
10
0.5t_c(SPC)M + 0.5t_c(LCO) -
10
0.5_tc(SPC)M + 0.5t_c(LCO) -
10
0.5t_c(SPC)M - 10
0.5t_c(SPC)M - 10
0.5t_c(SPC)M - 10
0.5t_c(SPC)M -10
35
MAX
127t_c(LCO)
0.5t_c(SPC)M - 0.5t_c(LCO)
0.5t_c(SPC)M - 0.5t_c(LCO
0.5t_c(SPC)M + 0.5t_c(LCO)
0.5t_c(SPC)M + 0.5t_c(LCO)
35
0.5t_c(SPC)M -10
0.5_tc(SPC)M -10
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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