PCI4410 Datasheet, PDF (150/201 Pages) Texas Instruments – PC Card and OHCI Controller

8.20 PCI Miscellaneous Configuration Register
The PCI miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 8–17 for
a complete description of the register contents.
Bit
31 30 29 28
Name
Type
R
R
R
R
Default 0
0
0
0
Bit
15 14 13 12
Name
Type
R/W R R/W R
Default 0
0
1
0
27 26 25 24 23 22 21 20 19 18 17 16
PCI miscellaneous configuration
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
11 10
9
8
7
6
5
4
3
2
1
0
PCI miscellaneous configuration
R R/W R
R
R
R
R R/W R/W R/W R/W R/W
0
1
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
PCI miscellaneous configuration
Read-only, Read/Write
F0h
0000 2400h
Table 8–17. PCI Miscellaneous Configuration Register
BIT
31–16
15
14
13
12–11
10
9–5
4
3
2
1
0
SIGNAL
RSVD
PME_D3COLD
RSVD
PME_SUPPORT_D2
RSVD
D2_SUPPORT
RSVD
DISABLE_PCI_
TARGET_ABORT
RSVD
DISABLE_SCLKGATE
DISABLE_PCIGATE
KEEP_PCLK
TYPE
R
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
FUNCTION
Reserved. These bits return 0s when read.
PME support from D3cold. This bit is used to program the corresponding read-only value read
from power management capabilities. This bit retains state through PCI reset and D3–D0
transitions.
Reserved. This bit returns 0 when read.
PME support. This bit is used to program the corresponding read-only value read from power
management capabilities. If wake up from the D2 power state implemented in PCI4410 is not
desired, then this bit may be reset to 0 to indicate to power management software that wake up
from D2 is not supported. This bit retains state through PCI reset and D3 – D0 transitions.
Reserved. These bits return 0s when read.
D2 support. This bit is used to program the corresponding read-only value read from power
management capabilities. If the D2 power state implemented in PCI4410 is not desired, then
this bit may be reset to 0 to indicate to power management software that D2 is not supported.
This bit retains state through PCI reset and D3–D0 transitions.
Reserved. Bits 9–5 return 0s when read.
When bit 4 is set to 1, the OSCI function returns indeterminate data instead of signaling target
abort. The default (0) allows the OSCI function to signal target abort.
Reserved. This bit defaults to 0.
When this bit is set to 1, the internal SCLK runs identically with the chip input.
When this bit is set to 1, the internal PCI clock runs identically with the chip input.
When this bit is set to 1, the PCI clock is always kept running through the CLKRUN protocol.
When reset to 0, the PCI clock may be stopped using CLKRUN.
8–14