TLC59208F_1 Datasheet, PDF (15/29 Pages) Texas Instruments – 8-BIT FM+ I2C BUS LED DRIVER

TLC59208F
www.ti.com .................................................................................................................................................................................................. SCLS715 – MARCH 2009
Individual Brightness Control Registers (PWM0–PWM7)
Table 6 describes the Individual Brightness Control Registers.
Table 6. PWM0–PWM7 – Individual Brightness Control Registers (Addresses 02h–09h) Bit Description
ADDRESS REGISTER
BIT
02h
PWM0
7:0
03h
PWM1
7:0
04h
PWM2
7:0
05h
PWM3
7:0
06h
PWM4
7:0
07h
PWM5
7:0
08h
PWM6
7:0
09h
PWM7
7:0
SYMBOL
IDC0[7:0]
IDC1[7:0]
IDC2[7:0]
IDC3[7:0]
IDC4[7:0]
IDC5[7:0]
IDC6[7:0]
IDC7[7:0]
ACCESS ⁽¹⁾
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VALUE
0000 0000⁽²⁾
0000 0000⁽²⁾
0000 0000⁽²⁾
0000 0000⁽²⁾
0000 0000⁽²⁾
0000 0000⁽²⁾
0000 0000⁽²⁾
0000 0000⁽²⁾
DESCRIPTION
PWM0 individual duty cycle
PWM1 individual duty cycle
PWM2 individual duty cycle
PWM3 individual duty cycle
PWM4 individual duty cycle
PWM5 individual duty cycle
PWM6 individual duty cycle
PWM7 individual duty cycle
(1) R = read, W = write
(2) Default value
A 97-kHz fixed-frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from
00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = LED output at maximum brightness). Applicable
to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0 and LEDOUT1 registers).
IDCx[7:0]
duty cycle = 256
Group Duty Cycle Control Register (GRPPWM)
Table 7 describes the Group Duty Cycle Control Register .
Table 7. GRPPWM – Group Duty Cycle Control Register (Address 0Ah) Bit Description
ADDRESS REGISTER
BIT
0Ah
GRPPWM
7:0
SYMBOL
GDC0[7:0]
ACCESS ⁽¹⁾
VALUE DESCRIPTION
R/W
1111 1111⁽²⁾ GRPPWM register
(1) R = read, W = write
(2) Default value
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed frequency signal is
superimposed with the 97 kHz individual brightness control signal. GRPPWM is then used as a global brightness
control allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a ‘Don’t
care’.
General brightness for the 8 outputs is controlled through 256 linear steps from 00h (0% duty cycle = LED output
off) to FFh (99.6% duty cycle = maximum brightness). Applicable to LED outputs programmed with LDRx = 11
(LEDOUT0 and LEDOUT1 registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers define a global blinking
pattern, where GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ contains
the blinking period (from 24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
GDC[7:0]
duty cycle = 256
Group Frequency Register (GRPFREQ)
Table 7 describes the Group Frequency Register.
ADDRESS
0Bh
Table 8. GRPFREQ – Group Frequency Register (Address 0Bh) Bit Description
REGISTER
BIT
SYMBOL ACCESS⁽¹⁾
VALUE DESCRIPTION
GRPFREQ
7:0
GFRQ[7:0]
R/W
0000 0000⁽²⁾ GRPFREQ register
(1) R = read, W = write
(2) Default value
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