TLC59208F_1 Datasheet, PDF (14/29 Pages) Texas Instruments – 8-BIT FM+ I2C BUS LED DRIVER

TLC59208F
SCLS715 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com
Mode Register 1 (MODE1)
Table 4 describes Mode Register 1.
Table 4. MODE1 – Mode Register 1 (Address 00h) Bit Description
BIT
SYMBOL
ACCESS ⁽¹⁾
VALUE DESCRIPTION
7
AI2
0 ⁽²⁾
Register auto-increment disabled
R
1
Register auto-increment enabled
6
AI1
0 ⁽²⁾
Auto-increment bit 1 = 0
R
1
Auto-increment bit 1 = 1
5
AI0
0 ⁽²⁾
Auto-increment bit 0 = 0
R
1
Auto-increment bit 0 = 1
4
SLEEP
R/W
0
Normal mode⁽³⁾
1 ⁽²⁾
Low power mode. Oscillator off⁽⁴⁾.
3
SUB1
R/W
0 ⁽²⁾
Device does not respond to I²C bus sub-address 1.
1
Device responds to I²C bus sub-address 1.
2
SUB2
R/W
0 ⁽²⁾
Device does not respond to I²C bus sub-address 2.
1
Device responds to I²C bus sub-address 2.
1
SUB3
R/W
0 ⁽²⁾
Device does not respond to I²C bus sub-address 3.
1
Device responds to I²C bus sub-address 3.
0
ALLCALL
R/W
0
Device does not respond to LED All Call I²C bus address.
1 ⁽²⁾
Device responds to LED All Call I²C bus address.
(1) R = read, W = write
(2) Default value
(3) It takes 500 µs max. for the oscillator to be up and running once SLEEP bit has been set from logic 1 to 0. Timings on LEDn outputs are
not guaranteed if PWMx, GRPPWM, or GRPFREQ registers are accessed within the 500 µs window.
(4) No LED control (on, off, blinking, or dimming) is possible when the oscillator is off. Write to a register cannot be accepted during SLEEP
mode. When you change the LED condition, SLEEP bit must be set to logic 0.
Mode Register 2 (MODE2)
Table 5 describes Mode Register 2.
Table 5. MODE2 – Mode Register 2 (Address 01h) Bit Description
BIT
SYMBOL
ACCESS ⁽¹⁾
VALUE DESCRIPTION
7:6
R
00⁽²⁾ Reserved
5
DMBLNK
R/W
0 ⁽³⁾
Group control = dimming
1
Group control = blinking
4
R
0 ⁽²⁾
Reserved
3
OCH
R/W
0 ⁽²⁾
Outputs change on Stop command⁽⁴⁾.
1
Outputs change on ACK.
2
WDT ENABLE
R/W
0 ⁽²⁾
Disable WDT
1
Enable WDT
00
5 ms
1:0
WDT PERIOD
R/W
01
10
11 ⁽²⁾
15 ms
25 ms
35 ms
(1) R = read, W = write
(2) Default value
(3) Default value
(4) Change of the outputs at the STOP command allows synchronizing outputs of more than one TLC59208F. Applicable to registers from
02h (PWM0) to 0Dh (LEDOUT) only.
14
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