TIBPAL16L8-7C Datasheet, PDF (15/23 Pages) Texas Instruments – HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X ™ PAL® CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
f_max SPECIFICATIONS
f_max without feedback, see Figure 3
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (t_su + t_h).
However, the minimum f_max is determined by the minimum clock period (t_w high + t_w low).
+ _{) )} Thus, fmax without feedback
1
(twhigh
twlow) ^or (tsu ¹
th).
CLK
LOGIC
ARRAY
C1
1D
tsu + th
or
tw high + tw low
Figure 3. f_max Without Feedback
f_max with internal feedback, see Figure 4
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
+ _{) * * Thus,} fmax with internal feedback
(tsu
1
tpd CLK to FB).
Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.
CLK
LOGIC
ARRAY
C1
1D
tsu
tpd CLK - to - FB
Figure 4. f_max With Internal Feedback
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