OPA333_15 Datasheet, PDF (15/33 Pages) Texas Instruments – 1.8-V, microPower, CMOS Operational Amplifiers, Zero-Drift Series

OPA333
OPA2333
www.ti.com
SBOS351D – MARCH 2006 – REVISED NOVEMBER 2013
LAYOUT GUIDELINES
GENERAL LAYOUT GUIDELINES
Attention to good layout practices is always recommended. Keep traces short and when possible, use a printed
circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible.
Place a 0.1-μF capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to
improve performance and provide benefits, such as reducing the electromagnetic interference (EMI)
susceptibility.
Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified
as a variation in offset voltage or dc signal levels with changes in the interfering RF signal. The OPA333 is
specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to
previous generation devices. Strong RF fields may still cause varying offset levels.
DFN PACKAGE
The OPA2333 is offered in an DFN-8 package (also known as SON). The DFN is a QFN package with lead
contacts on only two sides of the bottom of the package. This leadless package maximizes board space and
enhances thermal and electrical characteristics through an exposed pad.
DFN packages are physically small, have a smaller routing area, improved thermal performance, and improved
electrical parasitics. Additionally, the absence of external leads eliminates bent-lead issues.
The DFN package can be easily mounted using standard PCB assembly techniques. See Application Reports
SLUA271, QFN/SON PCB Attachment and SCBA017, Quad Flatpack No-Lead Logic Packages, both available
for download at www.ti.com.
NOTE
The exposed leadframe die pad on the bottom of the package should be connected to V–
or left unconnected.
DFN LAYOUT GUIDELINES
Solder the exposed leadframe die pad on the DFN package to a thermal pad on the PCB. A mechanical drawing
showing an example layout is attached at the end of this data sheet. Refinements to this layout may be
necessary based on assembly process requirements. Mechanical drawings located at the end of this data sheet
list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are
intended for use with thermal vias that connect the leadframe die pad to the heatsink area on the PCB.
Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push,
package shear, and similar board-level tests. Even with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: OPA333 OPA2333
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