DAC8811_15 Datasheet, PDF (15/29 Pages) Texas Instruments – DAC8811 16-Bit, Serial Input Multiplying Digital-to-Analog Converter

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DAC8811
SLAS411C – NOVEMBER 2004 – REVISED OCTOBER 2015
8.5 Programming
8.5.1 DAC8811 Input Shift Register
The DAC8811 has a 3-wire serial interface (CS, SCLK, and DIN) compatible with SPI, QSPI, and Microwire
interface standards, as well as most DSPs. See Figure 1 for an example of a typical write sequence.
The input shift register is 16 bits wide, as shown in Figure 25. The write sequence begins by bringing the CS line
low. Data from the DIN line are clocked into the 16-bit shift register on each falling edge of CLK. The serial clock
frequency can be as high as 50 MHz, making the DAC8811 compatible with high-speed DSPs. On the 16^th falling
edge of the serial clock, the last data bit is clocked in and the programmed function is executed.
At this point, the CS line may be kept low or brought high. In either case, it must be brought high for a minimum
of 20 ns before the next write sequence so that a falling edge of CS can initiate the next write sequence.
Figure 24. Data Input Register
DB15
DB0
D15 D15 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
CLK
SYNC
D_IN
DB15
DB0
Invalid Write Sequence:
SYNC HIGH before 16th Falling Edge
DB15
DB0
Valid Write Sequence:
Output Updates on 16th Falling Edge
Figure 25. SYNC Interrupt Facility
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