BQ2014H Datasheet, PDF (15/22 Pages) Texas Instruments – Low-Cost NiCd/NiMH Gas Gauge IC

Preliminary bq2014H
FLGS2 Bits
7
6
5
4
3
2
-
-
-
-
-
-
1
0
- OVLD
Program Pin Pull-Down Register (PPD)
The PPD register (address=07h) contains some of the pro-
gramming pin information for the bq2014H. The segment
drivers, SEG_1–5, have a corresponding PPD register loca-
tion, PPD_1–5. A given location is set if a pull-down resistor
has been detected on its corresponding segment driver.
For example, if SEG₁ and SEG₄ have pull-down resistors,
the contents of PPD are xxx01001.
Program Pin Pull-Up Register (PPU)
The PPU register (address=08h) contains the rest of the
programming pin information for the bq2014H. The seg-
ment drivers, SEG_1–5, have a corresponding PPU register
location, PPU_1–5. A given location is set if a pull-up resis-
tor has been detected on its corresponding segment driver.
For example, if SEG3 and SEG5 have pull-up resistors, the
contents of PPU are xxx10100.
PPD/PPU Bits
7
6
5
4
3
2
1
0
RSVD RSVD RSVD PPU₅ PPU4 PPU3 PPU2 PPU1
RSVD RSVD RSVD PPD₅ PPD4 PPD3 PPD2 PPD1
Capacity Inaccurate Count Register (CPI)
The CPI register (address=09h) is used to indicate the
number of times a battery has been charged without an
LMD update. Because the capacity of a rechargeable
battery varies with age and operating conditions, the
bq2014H adapts to the changing capacity over time. A
complete discharge from full (NAC ≥ 0.94 ∗ LMD) to
empty (EDV1=1) is required to perform an LMD update
assuming there have been no intervening valid charges,
the temperature is greater than or equal to 0°C, and
there has been no more than a 6% self-discharge
reduction.
The CPI register is incremented every time a valid
charge is detected. When NAC ≥ 0.94 _* LMD, however,
the CPI register increments on the first valid charge;
CPI does not increment again for a valid charge until
NAC < 0.94 _* LMD. This prevents continuous trickle
charging from incrementing CPI if self-discharge decre-
ments NAC. The CPI register increments to 255 with-
out rolling over. When the contents of CPI are incre-
mented to 64, the capacity inaccurate flag, CI, is as-
serted in the FLGS1 register. The CPI register is reset
whenever an update of the LMD register is performed,
and the CI flag is also cleared.
Battery Voltage Register (VSB)
The battery voltage register is used to read the single-cell
battery voltage on the SB pin. The VSB register (address
= 0Bh) is updated approximately once per second with the
present value of the battery voltage.
V_SB = 1.2V _* (VSB/256).
VSB Register Bits
7
6
5
4
3
2
1
0
VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0
Voltage Threshold Register (VTS)
The end-of-discharge threshold voltages (EDV1 and
EDVF) can be set using the VTS register (address =
0Ch). The VTS register sets the EDV1 trip point. EDVF
is set 25mV below EDV1. The default value in the VTS
register is A2h, representing EDV1 = 0.76V and EDVF =
0.735V. EDV1 = 1.2V _* (VTS/256).
VTS Register Bits
7
6
5
4
3
2
1
0
VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0
Compensated Available Charge Registers
(CACT/CACD)
The CACD register (address = 0Eh) contains the NAC
value compensated for discharge rate. This is a mono-
tonicly decreasing value during discharge. If the dis-
charge rate is > 2C then this value is lower than NAC.
CACD is updated only when the discharge rate compen-
sated NAC value is a lower value than CACD during
discharge. During charge, CACD is continuously up-
dated with the NAC value.
The CACT register (address = 0Dh) contains the CACD
value compensated for temperature. CACT will contain
a value lower than CACD when the battery temperature
is below 10°C. The CACT value is also used in calculat-
ing the LED display pattern.
Scaled Available Energy Registers
(SAEH/SAEL)
The SAEH high-byte register (address = 0Fh) and the
SAEL low-byte register (address = 10h) are used to scale
battery voltage and CACT to a value that can be trans-
lated to watt-hours remaining under the present condi-
tions.
Relative CAC Register (RCAC)
The RCAC register (address = 11h) provides the relative
battery state-of-charge by dividing CACT by LMD.
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