BQ2014H Datasheet, PDF (14/22 Pages) Texas Instruments – Low-Cost NiCd/NiMH Gas Gauge IC

bq2014H Preliminary
Table 9. Temperature Register
TMP3
0
0
0
0
0
0
0
0
1
1
1
1
1
TMP2
0
0
0
0
1
1
1
1
0
0
0
0
1
TMP1
0
0
1
1
0
0
1
1
0
0
1
1
0
TMP0
0
1
0
1
0
1
0
1
0
1
0
1
0
Temperature
T < -30°C
-30°C < T < -20°C
-20°C < T < -10°C
-10°C < T < 0°C
0°C < T < 10°C
10°C < T < 20°C
20°C < T < 30°C
30°C < T < 40°C
40°C < T < 50°C
50°C < T < 60°C
60°C < T < 70°C
70°C < T < 80°C
T > 80°C
Nominal Available Capacity Registers
(NACH/NACL)
The NACH high-byte register (address=03h) and the
NACL low-byte register (address=17h) are the main gas
gauging registers for the bq2014H. The NAC registers are
incremented during charge actions and decremented dur-
ing discharge and self-discharge actions. NACH and
NACL are set to 0 during a bq2014H reset.
Writing to the NAC registers affects the available charge
counts and, therefore, affects the bq2014H gas gauge opera-
tion. Do not write the NAC registers to a value greater than
LMD.
Battery Identification Register (BATID)
The BATID register (address=04h) is available for use
by the system to determine the type of battery pack.
The BATID contents are retained as long as V_RBI is
greater than 2V. The contents of BATID have no effect
on the operation of the bq2014H. There is no default
setting for this register.
Last Measured Discharge Register (LMD)
LMD is the register (address=05h) that the bq2014H
uses as a measured full reference. The bq2014H adjusts
LMD based on the measured discharge capacity of the
battery from full to empty. In this way the bq2014H up-
dates the capacity of the battery. LMD is set to PFC
during a bq2014H reset.
LMD is set to DCR upon the first valid charge after EDV
is set if VDQ is set.
If DCR < 0.94 LMD, then LMD is set to 0.94 ∗ LMD.
Secondary Status Flags Register (FLGS2)
The FLGS2 register (address=06h) contains the secon-
dary bq2014H flags.
Bit 7 and bit 1 of FLGS2 are reserved. Do not write to
these bits.
The discharge rate flags, DR2–0, are bits 6–4.
FLGS2 Bits
7
6
5
4
3210
-
DR2 DR1 DR0 - - -
They are used to determine the current discharge re-
gime as follows:
DR2
0
0
0
DR1
0
0
1
DR0
0
1
0
Discharge Rate
DRATE < 0.5C
0.5C ≤ DRATE < 2C
2C < DRATE
The enable interrupt flag (ENINT) is a test bit used to
determine V_SR activity sensed by the bq2014H. The
state of this bit will vary and should be ignored by the
system.
FLGS2 Bits
7
6
5
4
3
210
-
-
-
- ENINT - -
The valid charge flag (VQ), bit 2 of FLGS2, is used to
indicate whether the bq2014H recognizes a valid charge
condition. This bit is reset on the first discharge after
NAC = LMD.
The VQ values are
FLGS2 Bits
7
6
5
4
3
2
10
-
-
-
-
- VQ -
where VQ is
0 Valid charge action not detected between a
discharge from NAC = LMD and EDV1
1 Valid charge action detected
The overload flag (OVLD) is asserted when a discharge
rate in excess of 2C is detected. OVLD remains asserted
as long as the condition persists and is cleared 0.5 sec-
onds after the rate drops below 2C. The overload condi-
tion is used to stop sampling of the battery terminal char-
acteristics for end-of-discharge determination.
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