TSB12C01A Datasheet, PDF (14/59 Pages) Texas Instruments – High-Speed Serial-Bus Link-Layer Controller

2.1.3 Receiver
The receiver takes incoming data from the phy interface and determines if the incoming data is addressed
to this node. If the incoming packet is addressed to this node, the CRC of the packet is checked. If the header
CRC is good, the header is confirmed in the GRF. For block and isochronous packets, the remainder of the
packet is confirmed one quadlet at a time. The receiver places a status quadlet in the GRF after the last
quadlet of the packet is confirmed in the GRF. The status quadlet contains the error code for the packet. The
error code is the acknowledge code that is sent for that packet. For broadcast packets that do not need
acknowledge packets, the error code is the acknowledge code that would have been sent. This
acknowledge code tells the transaction layer whether or not the data CRC is good or bad. When the header
CRC is bad, the header is flushed and the rest of the packet is ignored.
When a cycle-start message is received, it is detected and the cycle-start message data is sent to the cycle
timer. The cycle-start messages are not placed in the GRF like other quadlet packets. At the end of an
isochronous cycle and if the cycle mark enable (CyMrkEn) bit of the control register is set , the receiver
inserts a cycle-mark packet in the GRF to indicate the end of the isochronous cycle.
2.1.4 Transmit and Receive FIFOs
The TSB12C01A contains two transmit FIFOs (asynchronous and isochronous) and one receive FIFO
(general receive). Each of these FIFOs is one quadlet wide and their length is software adjustable. These
software-adjustable FIFOs allow customization of the size of each FIFO for individual applications. The sum
of all FIFOs cannot be larger than 509 quadlets. To understand how to set the size of the FIFOs, see
subsections 3.2.11 through 3.2.13. The transmit FIFOs are write only from the host bus interface, and the
receive FIFO is read only from the host bus interface.
An example of how to use software-adjustable FIFOs follows:
In applications where isochronous packets are large and asynchronous packets are small, the implementer
can set the ITF and GRF to a large size (200 quadlets each) and set the ATF to a smaller size (100 quadlets).
Notice that the sum of all FIFOs is less than or equal to 509 quadlets.
2.1.5 Cycle Timer
The cycle timer is used by nodes that support isochronous data transfer. The cycle timer is a 32-bit
cycle-timer register. Each node with isochronous data-transfer capability has a cycle-timer register as
defined in the IEEE 1394-1995 standard. In the TSB12C01A, the cycle-timer register is implemented in the
cycle timer and is located in IEEE-1212 initial register space at location 200h and can also be accessed
through the local bus at address 14h. The low-order 12 bits of the timer are a modulo 3072 counter, which
increments once every 24.576-MHz clock periods (or 40.69 ns). The next 13 higher-order bits are a count
of 8, 000-Hz (or 125 µs)cycles, and the highest 7 bits count seconds.
The cycle timer contains the cycle-timer register. The cycle-timer register consists of three fields: cycle
offset, cycle count, and seconds count. The cycle timer has two possible sources. First, if the cycle source
(CySrc) bit in the configuration register is set, then the CYCLEIN input causes the cycle count field to
increment for each positive transition of the CYCLEIN input (8 kHz) and the cycle offset resets to all zeros.
CYCLEIN should only be the source when the node is cycle master. When the cycle-count field increments,
CYCLEOUT is generated. The timer can also be disabled using the cycle-timer-enable bit in the control
register. See subsection 3.2.5 for more information.
The second cycle-source option is when the CySrc bit is cleared. In this state, the cycle-offset field of the
cycle-timer register is incremented by the internal 24.576-MHz clock. The cycle timer is updated by the
reception of the cycle-start packet for the noncycle master nodes. Each time the cycle-offset field rolls over,
the cycle-count field is incremented and the CYCLEOUT signal is generated. The cycle-offset field in the
cycle-start packet is used by the cycle-master node to keep all nodes in phase and running with a nominal
isochronous cycle of 125 µs.
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