TMS626812 Datasheet, PDF (14/40 Pages) Texas Instruments – 1048576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
interrupted bursts (continued)
nCCD = Two Cycles
CLK
WRT Command
at Column
Address C0
Interrupting
WRT Command
at Column Address C1
DQ
C0
C0 + 1
C1
C1 + 1
C1 + 2
NOTE A: For this example, assume burst length = 4.
Figure 6. Write Burst Interrupted by Write Command
C1 + 3
CLK
DQ
DQM
nCCD = Three Cycles
WRT Command
D
D
Interrupting
DEAC or DCAB
Command
Ignored
Ignored
tWR
NOTE A: For this example assume burst length = 4.
Figure 7. Write Burst Interrupted by DEAC/DCAB Command
power up
Device initialization should be performed after a power up to the full V_CC level. After power is established, a
200-µs interval is required (with no inputs other than CLK). After this interval, both banks of the device must be
deactivated. Eight REFR commands must be performed and the mode register must be set to complete the
device initialization.
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