TMS626812 Datasheet, PDF (1/40 Pages) Texas Instruments – 1048576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
D Organization . . . 1M × 8 × 2 Banks
D 3.3-V Power Supply (± 10% Tolerance)
D Two Banks for On-Chip Interleaving
(Gapless Accesses)
D High Bandwidth – Up to 83-MHz Data Rates
D CAS Latency Programmable to 2 or 3
Cycles From Column-Address Entry
D Burst Sequence Programmable to Serial or
Interleave
D Burst Length Programmable to 1, 2, 4, or 8
D Chip Select and Clock Enable for
Enhanced-System Interfacing
D Cycle-by-Cycle DQ-Bus Mask Capability
D Auto-Refresh and Self-Refresh Capability
D 4K Refresh (Total for Both Banks)
D High-Speed, Low-Noise Low-Voltage TTL
(LVTTL) Interface
D Power-Down Mode
D Compatible With JEDEC Standards
D Pipeline Architecture
D Temperature Ranges
Operating, 0°C to 70°C
Storage, – 55°C to 150°C
D Performance Ranges:
DGE PACKAGE
( TOP VIEW )
V_CC 1
DQ0 2
V_SSQ 3
DQ1 4
V_CCQ 5
DQ2 6
V_SSQ 7
DQ3 8
V_CCQ 9
NC 10
NC 11
W 12
CAS 13
RAS 14
CS 15
A11 16
A10 17
A0 18
A1 19
A2 20
A3 21
V_CC 22
44 V_SS
43 DQ7
42 V_SSQ
41 DQ6
40 V_CCQ
39 DQ5
38 V_SSQ
37 DQ4
36 V_CCQ
35 NC
34 NC
33 DQM
32 CLK
31 CKE
30 NC
29 A9
28 A8
27 A7
26 A6
25 A5
24 A4
23 V_SS
SYNCHRONOUS
CLOCK CYCLE
TIME
tCK3
tCK2
(CL = 3) (CL = 2)
ACCESS TIME
CLOCK TO
OUTPUT
tCK3
tCK2
(CL = 3) (CL = 2)
’626812-12A† 12 ns
15 ns
9 ns
9 ns
’626812-12
12 ns
18 ns
9 ns
10 ns
† _{–12A speed device is supported only at –5/+10% VCC}
REFRESH
INTERVAL
64 ms
64 ms
description
The TMS626812 is a high-speed 16 777 216-bit
synchronous dynamic random access memory
(SDRAM) device organized as two banks of
1 048 576 words with eight bits per word.
All inputs and outputs of the TMS626812 series
are compatible with the LVTTL interface.
PIN NOMENCLATURE
A0 – A10 Address Inputs
A0 – A10 Row Addresses
A0 – A8 Column Addresses
A10 Automatic-Precharge Select
A11
Bank Select
CAS Column-Address Strobe
CKE Clock Enable
CLK System Clock
CS
Chip Select
DQ0 – DQ7
SDRAM Data Input / Output
DQM Data / Output Mask Enable
NC
No External Connect
RAS Row-Address Strobe
VCC
VCCQ
VSS
VSSQ
W
Power Supply (3.3-V Typ)
Power Supply for Output Drivers (3.3-V Typ)
Ground
Ground for Output Drivers
Write Enable
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
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