TMS370C736AFNT Datasheet, PDF (14/49 Pages) Texas Instruments – 8-BIT MICROCONTROLLER

TMS370Cx36
8-BIT MICROCONTROLLER
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
interrupts (continued)
Table 7. Hardware System Interrupts
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _INTERRUPT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _SOURCE
INTERRUPT
FLAG
OSC FLT FLG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _RESET
External RESET
Watchdog Overflow
Oscillator Fault
COLD START
(No Flag)
OSC FLT FLAG
INT1
External Interrupt 1
INT1 FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _SPI
SPI RX/TX Complete
SPI INT FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{PACT Circular Buffer}
Buffer Half/Full
Interrupt Flag
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{PACT CP6 Event}
CP6 INT FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{PACT CP5 Event}
CP5 INT FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{PACT (Group 1)}
PACT CP4 Event
PACT CP3 Event
CP4 INT FLAG
CP3 INT FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{PACT CP2 Event}
CP2 INT FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{PACT CP1 Event}
CP1 INT FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Default Timer}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _Overflow
DEFTIM OVRFL INT
FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{PACT (Group 2)}
PACT SCI Rx Int
PACT SCI Tx Int
PACT RX RDY
PACT TX RDY
PACT Cmd/Def Entry 0
CMD/DEF INT 0 FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{PACT Cmd/Def Entry 1}
CMD/DEF INT 1 FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{PACT Cmd/Def Entry 2}
CMD/DEF INT 2 FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{PACT (Group 3)}
PACT Cmd/Def Entry 3
PACT Cmd/Def Entry 4
CMD/DEF INT 3 FLAG
CMD/DEF INT 4 FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{PACT Cmd/Def Entry 5}
CMD/DEF INT 5 FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PACT Cmd/Def Entry 6
CMD/DEF INT 6 FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{PACT Cmd/Def Entry 7}
CMD/DEF INT 7 FLAG
ADC1
ADC1 Conversion Complete AD INT FLAG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{†Relative priority within an interrupt level}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{‡Release microcontroller from STANDBY and HALT low-power modes}
SYSTEM
INTERRUPT
RESET†
INT1‡
SPIINT
BUFINT
CP6INT
CP5INT
CP4INT
CP3INT
CP2INT
CP1INT
POVRL
INT
PRXINT
PTXINT
CDINT 0
CDINT 1
CDINT 2
CDINT 3
CDINT 4
CDINT 5
CDINT 6
CDINT 7
ADINT
VECTOR
ADDRESS
MODULE
PRIORITY†
PRIORITY
IN
GROUP
7FFEh, 7FFFh
1
7FFCh, 7FFDh
2
7FF6h, 7FF7h
3
7FB0h, 7FB1h
1
7FB2h, 7FB3h
2
7FB4h, 7FB5h
3
7FB6h, 7FB7h
4
4
7FB8h, 7FB9h
5
7FBAh, 7FBBh
6
7FBCh, 7FBDh
7
7FBEh, 7FBFh
8
7F9Eh, 7F9Fh
1
5
7F9Ch, 7F9Dh
2
7FA0h, 7FA1h
1
7FA2h, 7FA3h
2
7FA4h, 7FA5h
3
7FA6h, 7FA7h
4
6
7FA8h, 7FA9h
5
7FAAh, 7FABh
6
7FACh, 7FADh
7
7FAEh, 7FAFh
8
7FECh, 7FEDh
7
privileged operation and EEPROM write protection override
The TMS370Cx36 family is designed with significant flexibility to enable the designer to software-configure the
system and peripherals to meet the requirements of a variety of applications. The nonprivileged mode of
operation ensures the integrity of the system configuration, once it is defined for an application. Following a
hardware reset, the TMS370Cx36 operates in the privileged mode, where all peripheral file registers have
unrestricted read / write access, and the application program configures the system during the initialization
sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is
set to 1 to enter the nonprivileged mode, disabling write operations to specific configuration-control bits within
the PF. Table 8 lists the control bits shown in the table which are write-protected during the nonprivileged mode
and must be configured by software prior to exiting the privileged mode.
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