TLC5905 Datasheet, PDF (14/27 Pages) Texas Instruments – LED DRIVER

TLC5905
LED DRIVER
SLLS401 – NOVEMBER 1999
PRINCIPLES OF OPERATION
shift register latch for brightness control and OVM
The shift register latch for both the brightness control and OVM (output voltage monitor) is configured with a
1 x 1 byte. In the shift register latch for brightness control, the division ratio of GSCLK can be set and the output
current value on constant current output can be adjusted. In the shift register latch for OVM, the comparison
voltage at the OVM comparator on constant current output terminals (OUT0 to OUT15) can be set and the output
signal for both XDOWN1 and XDOWN2 can be forced to a low level. When powered up, the latch data is
indeterminate and shift register is not initialized. When these functions are used, data should be written to the
shift register latch prior to turning the constant current output on (BLANK=L). Also, it is inhibited from rewriting
the latch value for brightness control when the constant current output is turned on. When these functions are
not used, latch value can be set to the default value setting of BCENA or MCENA or to low level (tied to GND).
The configuration of the shift register and latch for brightness control and monitor control is shown in Figure 4.
XLATCH
Latch for Brightness Control
GSCLK Division Ratio Data Set
0
MSB
0
0
LSB
Current Data Adjusted On Constant Current Output
1
1
1
1
1
MSB
LSB
(see Note)
SOUT
Shift Register for Brightness Control
8th bit 7th bit
6th bit 5th bit
4th bit 3rd bit 2nd bit
1st bit
SCLK
SIN
Latch for OVM
XLATCH
N/A
0
MSB
Monitor Control Data
0
0
1
LSB
(see Note)
SOUT
Shift Register for OVM
8th bit 7th bit
6th bit 5th bit
4th bit 3rd bit 2nd bit
1st bit
SCLK
SIN
NOTE: Indicates default value at BCENA low if brightness control latch, at MCENA low if OVM latch.
Figure 4. Relationship Between Shift Register and Latch for Brightness Control and OVM
write data to shift register latch
The shift register latch written is selected using the RSEL0 and RSEL1 terminal. The data is applied to the SIN
data input terminal and clocked into the shift register synchronizing to the rising edge of SCLK after XENABLE
is pulled low. The shift register for gray scale data is 64 bit length in the 8 bit mode resulting in 64 times of SCLK,
and 128 bit length in the16 bit mode resulting in 128 times of SCLK. Brigtness control and monitor control results
in eight times the SCLK input. At number of SCLK input for each case, data can be written into the shift register.
In this condition, when XLATCH is pulled high, data in the shift register is clocked into latch (data through), and
when XLATCH is pulled low, data is held (latch).
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