TLC5615C Datasheet, PDF (14/18 Pages) Texas Instruments – 10-BIT DIGITAL-TO-ANALOG CONVERTERS

TLC5615C, TLC5615I
10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS142C – OCTOBER 1996 – REVISED MARCH 2000
APPLICATION INFORMATION
linearity, offset, and gain error using single ended supplies (continued)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage. For the
TLC5615, the zero-scale (offset) error is plus or minus 3 LSB maximum. The code is calculated from the
maximum specification for the negative offset.
power-supply bypassing and ground management
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground
currents are well managed and there are negligible voltage drops across the ground plane.
A 0.1-µF ceramic-capacitor bypass should be connected between V_DD and AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the
digital power supply.
Figure 15 shows the ground plane layout and bypassing technique.
Analog Ground Plane
1
8
2
7
3
6
4
5
0.1 µF
Figure 15. Power-Supply Bypassing
saving power
Setting the DAC register to all 0s minimizes power consumption by the reference resistor array and the output
load when the system is not using the DAC.
ac considerations
digital feedthrough
Even with CS high, high-speed serial data at any of the digital input or output terminals may couple through the
DAC package internal stray capacitance and appear at the DAC analog output as digital feedthrough. Digital
feedthrough is tested by holding CS high and transmitting 0101010101 from DIN to DOUT.
analog feedthrough
Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog
feedthrough is tested by holding CS high, setting the DAC code to all 0s, sweeping the frequency applied to
REFIN, and monitoring the DAC output.
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