TLC320AD57C Datasheet, PDF (14/21 Pages) Texas Instruments – Sigma-Delta Stereo Analog-to-Digital Converter

2.8.2 Slave Mode
As a slave, the TLC320AD57C receives LRClk, Fsync, and SCLK as inputs. The conversion cycle
synchronizes to the rising edge of LRClk, and the data synchronizes to the falling edge of SCLK. SCLK must
meet the setup time requirements specified in Section 3.2, Recommended Operating Conditions.
Synchronization of the slave modes is accomplished with the digital power-down control.
In slave mode, Fsync is an input. Three modes are provided as shown in Figures 2–4(a) through 2–4(c).
SCLK and LRClk are externally generated and sourced. The first rising edges of SCLK and LRClk after a
power-down cycle initiate the conversion cycle. Refer to Section 2.8.1, Master Mode for signal functions.
Several modes are available when the TLC320AD57C is configured as a slave. Using the Mode0, Mode1,
and Mode2 terminals, the TLC320AD57C can be set to shift out the MSB first or the LSB first [see Figures
2–4(a) and 2–4(b)]. The number of bits shifted out can be controlled by the number of valid SCLK cycles
provided within the left or right channel period. If only enough clocks are provided to shift out 16 data bits
before LRClk changes state, this is equivalent to a 16-bit mode.
Mode 000
SCLK
Fsync
DOUT
input
input
output
LRClk input
(a) SLAVE MODE (Fsync high)
17 16 ^{. . .} 1 0
Left
17 16 ^{. . .} 1 0
32 – 128 SCLKs
Right
Mode 001
SCLK
Fsync
DOUT
LRClk
Mode 010
SCLK
Fsync(1)
DOUT(1)
Fsync(2)
DOUT(2)
LRClk
(b) SLAVE MODE (Fsync high)
0 1 . . . 16 17
0 1 . . . 16 17
64 SCLKs
Left
Right
(c) SLAVE MODE (Fsync controlled)
17
...
0
17
...
0
17
...
Left
0
17
32 – 128 SCLKs
Right
...
0
Figure 2–4. Serial Slave Transfer Modes
2–6