TIBPAL20L8-15C Datasheet, PDF (14/17 Pages) Texas Instruments – HIGH-PERFORMANCE IMPACT E PAL CIRCUITS

TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT ™ PAL^® CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of V_CC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.
VCC
4V
5V
Active Low
Registered Output
CLK
tpd^†
(600 ns TYP, 1000 ns MAX)
1.5 V
tsu^‡
1.5 V
tw
VOH
VOL
VIH
1.5 V
VIL
† _{This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.}
‡ _{This is the setup time for input or feedback.}
Figure 2. Power-Up Reset Waveforms
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