THS1050 Datasheet, PDF (14/20 Pages) Texas Instruments – 10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER

THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278 – APRIL 2000
APPLICATION INFORMATION
using the THS1050 references
The option of internal or external reference is provided by allowing for an external connection of the internal
reference to the reference inputs. This type of reference selection offers the lowest noise possible by not relying
on any active switch to make the selection. Compensating each reference output with a 1-µF and 0.01-µF chip
capacitor is required as shown in Figure 18. The differential analog input range is equal to
2 (V_REFOUT+ – V_{REFOUT–)}. When using external references, it is best to decouple the reference inputs with a
0.1-µF and 0.01-µF chip capacitor as shown in Figure 19.
VREFIN+
VREFOUT+
External Reference +
VREFIN+
0.01 µF
1 µF
0.01 µF
1 µF
VREFIN–
VREFOUT–
0.01 µF 0.1 µF
External Reference –
0.01 µF 0.1 µF
VREFIN–
Figure 18. Internal Reference Usage
Figure 19. External Reference Usage
using the THS1050 clock input
The THS1050 is a high performance A/D converter. In order to obtain the best possible performance, care
should be taken to ensure that the device is clocked appropriately. The optimal clock to the device is a low jitter
square wave with sharp rise times (< 2ns) at 50% duty cycle. The two clock inputs (CLK+ and CLK–), should
be driven with complementary signals that have minimal skew, and nominally swing between 0 V and 5 V. The
device will still operate with a peak-to-peak swing of 3 V on each clock channel (around the 2.5 V midpoint).
Use of a transformer coupled clock input ensures minimal skew between the CLK+ and CLK– signals. If the
available clock signal swing is not adequate, a step-up transformer can be used in order to deliver the required
levels to the converter’s inputs, see Figure 20. For example if a 3.3 V standard CMOS logic is used for clock
generation, a minicircuits T4 –1H transformer can be used for 2x voltage step-up. This provides greater than
6-V differential swing at the secondary of the transformer, which provides greater than 3-V swings to both CLK+
and CLK– terminals of THS1050. The center tap of the transformer secondary is connected to the V_CM terminal
of the THS1050 for proper dc biasing.
Both the transformer and the clock source should be placed close to THS1050 to avoid transmission line effects.
3.3 V TTL logic is not recommended with T4 –1H transformer due to TTLs tendency to have lower output swings.
If the input to the transformer is a square wave (such as one generated by a digital driver), care must be taken
to ensure that the transformer’s bandwidth does not limit the signal’s rise time and effectively alter its shape and
duty cycle characteristics. For a 50 MSPS rate, the transformer’s bandwidth should be at least 300 MHz. A low
phase noise sinewave can also be used to effectively drive the THS1050. In this case, the bandwidth of the
transformer becomes less critical, as long as it can accommodate the frequency of interest (for example,
50 MHz). The turns ratio should be chosen to ensure appropriate levels at the device’s input. If the clock signal
is fed through a transmission line of characteristic impedance Zo, then the secondary of the transformer should
be terminated with a resistor of nZo, where n is the transformer’s impedance ratio (1:n) as shown in Figure 20.
Alternatively a series termination resistor having impedance equal to the characteristic impedance of the
transmission line can be used at the clock source.
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