SN74V263 Datasheet, PDF (14/52 Pages) Texas Instruments – 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
half-full flag (HF)
The HF output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO beyond half-full sets HF low.
The flag remains low until the difference between the write and read pointers becomes less than or equal to half
of the total depth of the device. The rising RCLK edge that accomplishes this condition sets HF high.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF goes low after [(D – 1)/2] + 2 writes
to the FIFO. If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the
SN74V273, D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both ×9 input and ×9 output bus
widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283,
and D = 131073 for the SN74V293.
In standard mode, if no reads are performed after reset (MRS or PRS), HF goes low after (D/2) + 1 writes to
the FIFO. If ×18 input or ×18 output bus width is selected, D = 8192 for the SN74V263, D = 16384 for the
SN74V273, D = 32768 for the SN74V283, and D = 65536 for the SN74V293. If both ×9 input and ×9 output bus
widths are selected, D = 16384 for the SN74V263, D = 32768 for the SN74V273, D = 65536 for the SN74V283,
and D = 131072 for the SN74V293.
See Figure 22 for timing information. Because HF is updated by both RCLK and WCLK, it is considered
asynchronous.
data outputs (Q0–Qn)
Q0–Q17 are data outputs for 18-bit-wide data or Q0–Q8 are data outputs for 9-bit-wide data.
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