SM72445_15 Datasheet, PDF (14/20 Pages) Texas Instruments – SM72445 Programmable Maximum Power Point Tracking Controller With Adjustable PWM Frequency

SM72445
SNVS795 – MARCH 2012
www.ti.com
To run the system in Open Loop configuration, the Soft Reset bit must be set then cleared. The ADC channels
are inactive when the device is used in Open Loop configuration.
COMMUNICATING WITH THE SM72445
The SCL line is an input, the SDA line is bidirectional, and the device address can be set by the I2C0, I2C1 and
I2C2 pins. Three device address pins allow connection of up to 7 SM72445s to the same I2C master. A pull-up
resistor (10kΩ) to a 5V supply is used to set a bit 1 on the device address. Device addressing for slaves are as
follows:
I2C0
I2C1
I2C2
Hex
0
0
1
0x1
0
1
0
0x2
0
1
1
0x3
1
0
0
0x4
1
0
1
0x5
1
1
0
0x6
1
1
1
0x7
The data registers in the SM72445 are selected by the Command Register. The Command Register is offset
from base address 0xE0. Each data register in the SM72445 falls into one of two types of user accessibility:
1) Read only (Reg0, Reg1)
2) Write/Read same address (Reg3, Reg4, Reg5)
There are 7 bytes in each register (56 bits), and data must be read and written in blocks of 7 bytes. Figure 14
depicts the ordering of the bytes transmitted in each frame and the bits within each byte. In the read sequence
depicted in Figure 15 the data bytes are transmitted in Frames 5 through 11, starting from the LSByte, DATA1,
and ending with MSByte, DATA7. In the write sequence depicted in Figure 16, the data bytes are transmitted in
Frames 4 through 11. Only the 100kHz data rate is supported. Please refer to “The I2C Bus Specification”
version 2.1 (Doc#: 939839340011) for more documentation on the I2C bus.
7 Byte Data Frame:
DATA 1 DATA 2 DATA 3
LSByte
DATA 6 DATA 7
MSByte
Each Byte contains 8 bits data:
D7
D6
D5
MSBit
D1
D0
LSBit
Figure 14. Endianness Diagram
14
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